Ujjwal Guin, Ph.D., IEEE Senior Member

Godbold Associate Professor
Department of Electrical and Computer Engineering
Auburn University
325 Broun Hall, Auburn, AL 36849-5201, USA
Email: ujjwal.guin at auburn dot edu
Phone: (334) 844-1835 (Office)
[Curriculum vitae][Google Scholar][Research Gate]

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Books
  1. M. Tehranipoor, U. Guin, and D. Forte, "Counterfeit Integrated Circuits: Detection and Avoidance," Springer, 2015. [Amazon] [BibTeX: tehranipoor2015counterfeit]
Book Chapters
  1. P. Cui, U. Guin, and M. Tehranipoor, "Trillion Sensors Security," in Emerging Topics in Hardware Security, Springer, 2021. [Springer] [BibTeX: cui2021trillion]
  2. U. Guin, and M. Tehranipoor, "Obfuscation and Encryption for Securing Semiconductor Supply Chain," in Hardware Protection through Obfuscation, Springer, 2017. [Springer] [BibTeX: guin2017obfuscation]
Patents
  1. M. Tehranipoor, D. Forte, and U. Guin, "A comprehensive framework for protecting intellectual property in the semiconductor industry," 2017, US2017/037403, WO2017218631 A2. [LINK] [BibTeX: tehranipoor2017comprehensive]
Journal Papers (Accepted)
  1. Y. Zhong, and U. Guin, "A Comprehensive Test Pattern Generation Approach Exploiting SAT Attack for Logic Locking," in IEEE Transactions on Computers, pp. 1-11, 2023. [LINK] [BibTeX: zhong2023comprehensive]
  2. Y. Zhong, and U. Guin, "Complexity Analysis of the SAT Attack on Logic Locking," in IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD), pp. 1-14, 2023. [LINK][PDF] [BibTeX: zhong2023complexity]
  3. Y. Zhong, A. Jain, M.T. Rahman, N. Adadi, J. Xie, and U. Guin, "AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 1-17, 2022. [arXiv LINK] [BibTeX: zhong2022afia]
  4. W. Wang, A. D. Singh, and U. Guin, "A Systematic Bit Selection Method for Robust SRAM PUFs," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 301-311, 2022. [LINK] [PDF] [BibTeX: wang2022systematic]
  5. B. J. Lucas, A. Alwan, M. Murzello, Y. Tu, P. He, A. J. Schwartz, D. Guevara, U. Guin, K. Juretus, and J. Xie, "Lightweight Hardware Implementation of Binary Ring-LWE PQC Accelerator," in IEEE Computer Architecture Letters, pp. 17-20, 2022. [Link] [PDF] [BibTeX: lucas2022lightweight]
  6. Z. Collier, U. Guin, J. Sarkis, and J. Lambert, "Decision Model with Quantification of Buyer-Supplier Trust in Advanced Technology Enterprises," in Benchmarking: an International Journal, pp. 1-24, 2021. [Link] [PDF] [BibTeX: collier2021decision]
  7. C. Tang, L. Alahmed, J. Xu, M. Shen, N. A. Jones, M. Sadi, U. Guin, W. Zhao, and P. Li, "Effects of temperature and structural geometries on a skyrmion logic gate," in IEEE Transactions on Electron Devices (TED), pp. 1706-1712, 2021. [Link] [PDF] [BibTeX: tang2021effects]
  8. D. DiMase, Z. A. Collier, J. Muldavin, J. A. Chandy, D. Davidson, D. Doran, U. Guin, J. Hallman, J. Heebink, E. Hall, and Honorable A. R. Shaffer, "Zero Trust for Hardware Supply Chains: Challenges in Application of Zero Trust Principles to Hardware," in National Defense Industrial Association (NDIA), pp. 1-53, 2021. [White Paper] [LINK] [BibTeX: collier2021zero]
  9. P. He, U. Guin, and J. Xie, "Novel Low-Complexity Polynomial Multiplication over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), pp. 383-394, 2021. [Link] [PDF] [BibTeX: he2021novel]
  10. M. Sadi, and U. Guin, "Test and Yield Loss Reduction of AI and Deep Learning Accelerators," IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD), pp. 104-115, 2021. [Link] [BibTeX: sadi2021test]
  11. P. Chowdhury, U. Guin, A. D. Singh, and V. D. Agrawal, "Estimating Operational Age of an Integrated Circuit," in Journal of Electronic Testing: Theory and Applications (JETTA), pp. 1-16, 2021. [PDF] [BibTeX: chowdhury2021estimating]
  12. A. Jain, Z. Zhou and U. Guin, "TAAL: Tampering Attack on Any Key-based Logic Locked Circuits," in ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1-22, 2021. [PDF] [BibTeX: jain2021taal]
  13. Y. Zhang, A. Jain, P. Cui, Z. Zhou, and U. Guin, "A Novel Topology-Guided Attack and Its Countermeasure Towards Secure Logic Locking," Journal of Cryptographic Engineering, pp. 1-14, 2020. [LINK] [PDF] [BibTeX: zhang2020novel]
  14. W. Wang, U. Guin, and A. D. Singh, "Aging-Resilient SRAM-based Ture Random Number Generator for Lightweight Devices," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 301-311, 2020. [LINK] [PDF] [BibTeX: wang2020aging]
  15. J. Mahmod, and U. Guin, "Robust, Low-Cost and Secure Authentication Scheme for IoT Applications," Cryptography, pp. 1-20, 2020. [LINK] [PDF] [BibTeX: mahmod2020robust]
  16. P. Cui, J. Dixon, U. Guin, and D. DiMase, "A Blockchain-Based Framework for Supply Chain Provenance," IEEE Access, pp. 157113-157125, 2019. [LINK] [PDF] [BibTeX: cui2019blockchainProvenance]
  17. P. Cui, U. Guin, A. Skjellum, and D. Umphress, "Blockchain in IoT: Current Trends, Challenges and Future Roadmap," Journal of Hardware and Systems Security (HaSS), pp. 338-364, 2019. [LINK] [PDF] [BibTeX: cui2019blockchainSurvey]
  18. Y. Zhang and U. Guin, "End-to-End Traceability of ICs in Component Supply Chain for Fighting Against Recycling," Transactions on Information Forensics & Security (TIFS), pp. 767-775, 2019. [LINK] [PDF] [BibTeX: zhang2019end]
  19. U. Guin, N. Asadizanjani, and M. Tehranipoor "Standards for Hardware Security," GetMobile: Mobile Computing and Communications, pp. 5-9, 2019. [LINK] [PDF] [BibTeX: guin2019standards]
  20. B. Cyr, J. Mahmod, and U. Guin, "Low-Cost and Secure Firmware Obfuscation Method for Protecting Electronic Systems from Cloning," IEEE Internet of Things Journal, pp. 3700-3711, 2019. [LINK] [PDF] [BibTeX: cyr2019low]
  21. S. Wang, A. Ali, U. Guin, and A. Skjellum, "IoTCP: A Novel Trusted Computing Protocol for IoT," Journal of The Colloquium for Information System Security Education (CISSE), pp. 165-180, 2018. [LINK] [BibTeX: wang2018iotcp]
  22. U. Guin, Z. Zhou, and A. Singh, “Robust Design-for-Security (DFS) Architecture for Enabling Trust in IC Manufacturing and Test," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 818-830, 2018. [LINK] [PDF] [BibTeX: guin2018robust]
  23. M. Alam, M. Tehranipoor, and U. Guin, “TSensors Vision, Infrastructure and Security Challenges in Trillion Sensor Era: Current Trends and Future Directions," Journal of Hardware and Systems Security (HaSS), pp. 311-327, 2017. [LINK] [PDF] [BibTeX: alam2017tsensors]
  24. M. Tehranipoor, U. Guin, and S. Bhunia, “Invasion of the Hardware Snatchers: Cloned Electronics Pollute the Market," IEEE Spectrum, pp. 36-41, 2017. [LINK] [BibTeX: tehranipoor2017invasion]
  25. U. Guin, S. Bhunia, D. Forte, and M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware," IEEE Transactions on Dependable and Secure Computing (TDSC), pp. 265-278, 2016. [LINK] [PDF] [BibTeX: guin2016sma]
  26. U. Guin, Q. Shi, D. Forte, and M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs," ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1-20, 2016. [LINK] [PDF] [BibTeX: guin2016fortis]
  27. U. Guin, D. Forte, and M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for protecting Integrated Circuits against Recycling," IEEE Transactions on VLSI Systems (TVLSI), pp. 1233-1246, 2015. [LINK] [PDF] [BibTeX: guin2015design]
  28. U. Guin, K. Huang, D. DiMase, J. M. Carulli Jr., M. Tehranipoor, and Y. Makris, “Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain," Proceedings of the IEEE, pp. 1207-1228, 2014. [LINK] [PDF] [BibTeX: guin2014counterfeitProc] (cited in "White House 100-Day Reviews under Executive Order 14017" on "Building Resilient Supply Chains, Revitalizing American Manufacturing, and Fostering Broad-Based Growth")
  29. U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 9-23, 2014. [LINK] [PDF] [BibTeX: guin2014counterfeitJETTA] (Most downloaded article in 2014)
  30. U. Guin, D. DiMase, and M. Tehranipoor, “A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 25-40, 2014. [LINK] [PDF] [BibTeX: guin2014comprehensive]
Conference Papers
  1. A. P. Saha and U. Guin, “Optimizing Supply Chain Management using Permissioned Blockchains,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1-7, 2024. [PDF][BibTeX: saha2024optimizing]
  2. Z. T. Tisha, J. Muldavin and U. Guin, “Exploring Security Solutions and Vulnerabilities for Embedded Non-Volatile Memories,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 1-6, 2024. [PDF][BibTeX: Tisha2024exploring]
  3. G. Odom, H. Mohanty U. Guin and B. Krishnamachari, “Blockchain-Enabled Whitelisting Mechanisms for Enhancing Security in 3D ICs,” in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2024. [PDF][BibTeX: odom2024blockchain]
  4. G. Odom, Z. T. Tisha and U. Guin, “A Novel Self-referencing Approach Using Memory Power-up States for Detecting COTS SRAMs,” in VLSI Test Symposium (VTS), pp. 1-7, 2024. [PDF] [BibTeX: odom2024novel]
  5. U. Guin and B. Krishnamachari, “Blockchain-enabled Whitelisting for securing 3D ICs,” in GOMACTech, 2024. [BibTeX: guin2024blockchain]
  6. G. Odom, Z. T. Tisha, and U. Guin, “Self-Referencing Electrical Tests using SRAM Power-up States for Detecting Recycled ICs,” in GOMACTech, 2024. [BibTeX: odom2024self]
  7. Y. Zhong, A. Ebrahim, U. Guin, and V. Menon, “A Modular Blockchain Framework for Enabling Supply Chain Provenance,” in IEEE Physical Assurance and Inspection of Electronics (PAINE), pp. 1-7, 2023. [LINK][PDF] [BibTeX: zhong2023blockchain]
  8. Y. Zhong, J. Hovanes and U. Guin, “On-Demand Device Authentication using Zero-Knowledge Proofs for Smart Systems,” in Great Lakes Symposium on VLSI (GLSVLSI), 2023. [LINK][PDF] [BibTeX: zhong2023ondemand]
  9. J. Hovanes, Y. Zhong, and U. Guin, “A Novel IoT Device Authentication Scheme Using Zero-Knowledge Proofs,” in GOMACTech, 2023. [BibTeX: hovanes2023novel]
  10. J. Hovanes, Y. Zhong, and U. Guin, “Beware of Discarding Used SRAMs: Information is Stored Permanently,” in IEEE Physical Assurance and Inspection of Electronics (PAINE), pp. 1-7, 2022. [PDF] [BibTeX: hovanes2022beware] (Best Paper Award)
  11. Y. Zhong, and U. Guin, “Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations,” in Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2022. [PDF] [BibTeX: zhong2022fault]
  12. Y. Zhong, and U. Guin, “Chosen-Plaintext Attack on Energy-Efficient Hardware Implementation of GIFT-COFB,” in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 1-4, 2022. [PDF] [BibTeX: zhong2022chosen]
  13. Y. Zhang, C. Tang, P. Li, and U. Guin, “CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs,” in Design Automation Conference (DAC), pp. 1-6, 2022. [PDF] [BibTeX: zhang2022camskygate]
  14. Z. Zhou, U. Guin, P. Li, and V. D. Agrawal, “Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits,” in VLSI Test Symposium (VTS), pp. 1-7, 2022. [PDF] [BibTeX: zhou2022fault]
  15. M. Sadi, P. Li, U. Guin, S. Walters, and D. DiMase, “Low Power, Rad-Hard, and Secure Polymorphic and Neuromorphic Designs using Skyrmions,” in GOMACTech, 2022. [BibTeX: sadi2022low]
  16. Y. Tu, P. He, U. Guin, and J. Xie, “Low-Complexity Implementation of Lightweight Ring-LWE based Post-Quantum Cryptography,” in GOMACTech, 2022.
  17. Pratiksha Mittal, Austin Walthall, Pinchen Cui, Anthony Skjellum and U. Guin, “A Blockchain-Based Contactless Delivery System for Addressing COVID-19 and Other Pandemics,” in IEEE Workshop on Blockchain Security, Application, and Performance (BSAP), pp. 1-6, 2021. [PDF] [BibTeX: mittal2021blockchain]
  18. Z. Zhou, U. Guin, P. Li and V. Agrawal, “Defect Characterization and Testing of Skyrmion-Based Logic Circuits,” in VLSI Test Symposium (VTS), pp. 1-7, 2021. [PDF] [BibTeX: zhou2021defect] (Best Paper Nomination)
  19. S. Kundu, K. Basu, M. Sadi, T. Titirsha, S. Song, A. Das and U. Guin, “Special Session: Reliability Analysis for AI/ML Hardware,” in VLSI Test Symposium (VTS), pp. 1-10, 2021. [PDF] [BibTeX: kundu2021special]
  20. A. Jain, Z. Zhou, and U. Guin, “Survey of Recent Developments for Hardware Trojan Detection,” in IEEE International Symposium on Circuits & Systems (ISCAS), pp. 1-5, 2021. [PDF] [BibTeX: jain2021survey]
  21. A. Jain, and U. Guin, “A Novel Tampering Attack on AES Cores with Hardware Trojans,” in ITC-Asia, pp. 77-82, 2020. [PDF] [BibTeX: jain2020novel]
  22. A. Jain, M. T. Rahman and U. Guin, “ATPG-Guided Fault Injection Attacks on Logic Locking,” in IEEE Physical Assurance and Inspection of Electronics (PAINE), pp. 1-6, 2020. [LINK] [PDF] [BibTeX: jain2020atpg]
  23. A. Stern, D. Mehta, S. Tajik, U. Guin, F. Farahmandi and M. Tehranipoor, “SPARTA-COTS: A Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits," in IEEE Physical Assurance and Inspection of Electronics (PAINE), pp. 1-6, 2020. [LINK] [PDF] [BibTeX: stern2020sparta]
  24. A. Jain, U. Guin, M. T. Rahman, N. Asadizanjani, D. Duvalsaint, and R. D. (Shawn) Blanton, “Special Session: Novel Attacks on Logic-Locking," in VLSI Test Symposium (VTS), pp. 1-10, 2020. [LINK] [PDF] [BibTeX: jain2020special]
  25. J. Xie, K. Basu, K. Gaj and U. Guin, “Special Session: The Recent Advance in Hardware Implementation of Post-Quantum Cryptography," in VLSI Test Symposium (VTS), pp. 1-10, 2020. [LINK] [PDF] [BibTeX: xie2020special]
  26. W. Wang, U. Guin, and A. Singh, “A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture," in VLSI Test Symposium (VTS), pp. 1-6, 2020. [LINK] [PDF] [BibTeX: wang2020zero]
  27. Y. Zhang, P. Cui, Z. Zhou, and U. Guin, “TGA: An Oracle-less and Topology-Guided Attack on Logic Locking," in Attacks and Solutions in Hardware Security (ASHES), pp. 75-83, 2019. [LINK] [PDF] [BibTeX: zhang2019tga]
  28. P. Cui and U. Guin, “Countering Botnet of Things using Blockchain-Based Authenticity Framework," in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 598-603, 2019. [LINK] [PDF] [BibTeX: cui2019countering]
  29. U. Guin, W. Wang, C. Harper, and A. D. Singh, “Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells," in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 72-80, 2019. [LINK] [PDF] [BibTeX: guin2019detecting]
  30. J. Mahmod, S. Millican, U. Guin, and V. D. Agrawal, “Special Session: Delay Fault Testing - Present and Future," in IEEE VLSI Test Symposium (VTS), pp. 1-10, 2019. [LINK] [PDF] [BibTeX: mahmod2019special]
  31. P. Chowdhury, U. Guin, A. D. Singh and V. D. Agrawal, “Two-Pattern ΔIDDQ Test for Recycled IC Detection," in International Conference on VLSI Design (VLSID), pp. 82-87, 2019. [LINK] [PDF] [BibTeX: chowdhury2019two]
  32. U. Guin, P. Cui, and A. Skjellum, “Ensuring Proof-of-Authenticity of IoT Edge Devices using Blockchain Technology," in IEEE International Conference on Blockchain, pp. 1042-1049, 2018. [LINK] [PDF] [BibTeX: guin2018ensuring]
  33. W. Wang, A. D. Singh, U. Guin, and A. Chatterjee, “Exploiting Power Supply Ramp Rate for Calibrating Cell Strength in SRAM PUFs," in IEEE Latin-American Test Symposium (LATS), pp. 1-6, 2018. [LINK] [PDF] [BibTeX: wang2018exploiting]
  34. M. Alam, S. Chowdhury, M. Tehranipoor, and U. Guin, “Robust, Low-Cost, and Accurate Detection of Recycled ICs using Digital Signatures," in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 209-214, 2018. [LINK] [PDF] [BibTeX: alam2018robust]
  35. Z. Zhou, U. Guin, and V. D. Agrawal, “Modeling and Test Generation for Combinational Hardware Trojans," in IEEE VLSI Test Symposium (VTS), pp. 1-6, 2018. [LINK] [PDF] [BibTeX: zhou2018modeling]
  36. U. Guin, A. D. Singh, M. Alam, J. Canedo, and A. Skjellum, “A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things," in International Conference on VLSI Design, pp. 85-90, 2018. [LINK] [PDF] [BibTeX: guin2018secure]
  37. U. Guin, “Efficient Strategies for Detection and Avoidance of Counterfeit ICs," IEEE North Atlantic Test Workshop (NATW), pp. 1-5, 2017. [PDF] [BibTeX: guinefficient]
  38. U. Guin, Z. Zhou, and A. D. Singh, “A Novel Design-for-Security (DFS) Architecture to Prevent Unauthorized IC Overproduction," IEEE VLSI Test Symposium (VTS), pp. 1-6, 2017. [LINK] [BibTeX: guin2017novel]
  39. B. Shakya, U. Guin, M. Tehranipoor and D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs," IEEE International Conference on Computer Design (ICCD), pp. 289-295, 2015. [LINK] [BibTeX: shakya2015performance]
  40. U. Guin, X. Zhang, D. Forte, and M. Tehranipoor, “Low-Cost On-Chip Structures for Combating Die and IC Recycling," Design Automation Conference (DAC), pp. 1-6, 2014. [LINK] [BibTeX: guin2014low]
  41. U. Guin, D. Forte, D. DiMase, and M. Tehranipoor, “Counterfeit IC Detection: Test Method Selection Considering Test Time, Cost, and Tiel Level Risk," GOMACTech, pp. 1-4, 2014. [PDF] [BibTeX: guin2014icdetect]
  42. U. Guin, D. Forte, and M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling," GOMACTech, pp. 1-3, 2014. [PDF] [BibTeX: guin2014cost]
  43. U. Guin, D. Forte, and M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign," IEEE Microprocessor Test Verification (MTV), pp. 89-94, 2013. [LINK] [BibTeX: guin2013anti]
  44. U. Guin, and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures," DMSMS, 2013. (Extended Abstract) [LINK] [BibTeX: guin2013cdir]
  45. U. Guin, T. Chakraborty, and M. Tehranipoor, “Functional Fmax Test-Time Reduction using Novel DFTs for Circuit Initialization," IEEE Int. Conference on Computer Design (ICCD), pp. 1-6, 2013. [LINK] [BibTeX: guin2013functional]
  46. U. Guin, T. Chakraborty, and M. Tehranipoor, “Novel DFTs for Circuit Initialization to Reduce Functional Fmax Test Time," IEEE North Atlantic Test Workshop (NATW), pp. 1-5, 2013. [PDF] [BibTeX: guin2013novel]
  47. U. Guin and M. Tehranipoor, “On Selection of Counterfeit IC Detection Methods," IEEE North Atlantic Test Workshop (NATW), pp. 1-5, 2013. [PDF] [BibTeX: guin2013selection] (Received Best Paper Award)
  48. U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment," GOMACTech, pp. 1-4, 2013. [PDF] [BibTeX: guin2013asses]
  49. N. Murphy, U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment," DMSMS & Standardization, 2012. [BibTeX: murphy2012asses]
  50. U. Guin and C. -H. Chiang, “Design for Bit Error Rate Estimation of High Speed Serial Links," IEEE VLSI Test Symposium (VTS), pp. 278-283, 2011. [LINK] [BibTeX: guin2011design]
Posters
  1. Y. Zhang, P. Cui, Z. Zhou, and U. Guin, “SAL: Function Search Attack on Logic Locked Circuits," International Test Conference, pp. 1-2, 2019. [PDF]
Technical Reports
  1. U. Guin, M. Tehranipoor, D. DiMase, and M. Megrdician, “Counterfeit IC Detection and Challenges Ahead," ACM SIGDA, pp. 1-5, 2013. [PDF] [BibTeX: guin2013counterfeit]
Thesis
  1. U. Guin, “Establishment of trust and integrity in modern supply chain from design to resign," PhD Thesis, University of Connecticut, CT, 2016. [LINK]
  2. U. Guin, “Design for Bit Error Rate Estimation of High Speed Serial Links," Masters Thesis, Temple University, PA, 2010.