Ujjwal Guin, Ph.D., IEEE Senior Member

Godbold Associate Professor
Department of Electrical and Computer Engineering
Auburn University
325 Broun Hall, Auburn, AL 36849-5201, USA
Email: ujjwal.guin at auburn dot edu
Phone: (334) 844-1835 (Office)
[Curriculum vitae][Google Scholar][Research Gate]

Design, Test, and Security of Skyrmion Logic Circuits


With rapid scaling, CMOS devices are approaching the limit of quantum-mechanical boundaries. Among other things, this has resulted in increased process variation and static power dissipation. Fortunately, spintronic devices offer a feasible choice for post-Moore devices, given the recent advances in their design and fabrication process. As a realizable and robust topological magnetic texture in real space, magnetic skyrmion offers an ideal platform for implementing various non-volatile logic designs and magnetic memories. For the past few years, technologists have been predicting the end of scaling. Of course, these predictions are a direct consequence of what has happened to the CMOS technology. The chip technology has advanced in three directions to combat the difficulties arising from scaling. First, improved fabrication methods have recently brought the feature size down to 2 nanometers. Second, new geometries, such as 3-D device structures of nanosheet or finFET and others, have evolved. Third, a shift from semiconductors to other materials and physical phenomena, such as magnetic skyrmion to construct switching devices has shown new possibilities.

Simulation Videos


  • Simulation for Traditional Logic Gates
    • OR Gate AND Gate Inverter Fanout

  • Simulation for Camouflaged Logic Gates
    • Simple 1: OR Gate Simple 1: AND Gate Simple 2: OR Gate Simple 2: Buffer
    Complex: OR Gate Complex: AND Gate Complex: Multiplexer Complex: Buffer

  • Simulation for Defects -- Stuck-at Faults
    • Broken Line Voids Over Etching 1 Over Etching 2

  • Simulation for Bridging Defects
    • Example 1 Example 2

Publications

Disclaimer: The pdf files (articles) are copyright protected. Retrieving, copying, or distributing these files are prohibited. You may, however, browse these articles in the same spirit as you read an article in a public library.

Journal Papers
  1. C. Tang, L. Alahmed, J. Xu, M. Shen, N. A. Jones, M. Sadi, Ujjwal Guin , W. Zhao, and P. Li, "Effects of temperature and structural geometries on a skyrmion logic gate," in IEEE Transactions on Electron Devices (TED), pp. 1706-1712, 2021 [Link] [PDF] [BibTeX: tang2021effects].
Conference Papers
  1. Y. Zhang, C. Tang, P. Li, and U. Guin , “CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs,” in Design Automation Conference (DAC), pp. 1-6, 2022. [PDF] [BibTeX: ]
  2. M. Sadi, P. Li, U. Guin, S. Walters, and D. DiMase, “Low Power, Rad-Hard, and Secure Polymorphic and Neuromorphic Designs using Skyrmions,” in GOMACTech, 2022.
  3. Z. Zhou, U. Guin , P. Li, and V. D. Agrawal, “Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits,” in VLSI Test Symposium (VTS), pp. 1-7, 2022. [PDF][BibTeX: zhou2022fault]
  4. Z. Zhou, U. Guin, P. Li and V. Agrawal, “Defect Characterization and Testing of Skyrmion-Based Logic Circuits,” in VLSI Test Symposium (VTS), pp. 1-7, 2021, [PDF] [BibTeX: zhou2021defect] (Best Paper Nomination).