Ujjwal Guin, Ph.D., IEEE Senior Member

Godbold Associate Professor
Department of Electrical and Computer Engineering
Auburn University
325 Broun Hall, Auburn, AL 36849-5201, USA
Email: ujjwal.guin at auburn dot edu
Phone: (334) 844-1835 (Office)
[Curriculum vitae][Google Scholar][Research Gate]


IP Piracy and IC Overproduction


The persistent trend of device scaling has enabled designers to fit more and more functionality on a system-on-chip (SoC) to reduce overall area and cost of an integrated circuits (ICs). As the complexity has grown exponentially, it is impossible to design a complete SoC by a design house alone. Therefore, the semiconductor industry has shifted gears to the concept of design reuse rather than designing the whole SoC from scratch. Nowadays, the SoC designers obtain licenses for various functional blocks (known as intellectual properties or IPs) for their SoCs to optimize the design process and decrease time-to-market. In parallel, the increased complexity of the fabrication process has resulted in a majority of SoC designers no longer maintaining a fabrication unit (or foundry) of their own. Building and maintaining such fabs for modern SoCs are reported to cost more than several billions of dollars and increasing as technology further scales. Given the increasing cost, the semiconductor business has largely shifted to a contract-foundry business model (horizontal business model) over the past two decades. In this business model, the SoC designers first get licenses for third-party IPs (3PIPs) to be used in their SoC designs, design the SoCs by integrating the various 3PIPs and then outsource the SoC design to the foundries and assemblies for fabrication and packaging to reduce time-to-market and manufacturing costs.

When an untrusted party overuses IPs, or overproduces ICs and sells in the open market, the IP owners or the SOC designers lose any possible revenue that could have been gained from those chips. However, an even bigger concern with these ICs is that of reliability. An IC that uses a pirated IP may create a backdoor to leak secret information to the attacker or disable a system at some critical point in time. In addition, overproduced ICs may simply end up in the market with minimal or no testing for reliability and functionality. These ICs may also find their way into the supply chain for many critical applications, which raises concerns for safety and reliability. Since these ICs have the same name of the SoC designers, their failure would also tarnish company reputation. In addition, an SoC designer may legally purchase a 3PIP core from an IP vendor and then make clones, or illegitimate copies of the original IP. Similarly, untrusted foundries may sell illegal copies of the GDSII files that they receive from SoC designers for fabrication. Further, the integrity of the IP may be at risk. An untrusted SoC designer can add some extra features to those 3PIPs to make them look like a different one and then sell them to another SoC designer. An untrusted SoC designer may also modify a 3PIP to introduce a backdoor or hardware Trojan into the chip.

Project Sponsors

We are thankful to our sponsors for supporting our research.

Publications

Disclaimer: The pdf files (articles) are copyright protected. Retrieving, copying, or distributing these files are prohibited. You may, however, browse these articles in the same spirit as you read an article in a public library.

Book Chapters
  1. U. Guin, and M. Tehranipoor, "Obfuscation and Encryption for Securing Semiconductor Supply Chain", in Hardware Protection through Obfuscation, Springer, 2017. [Springer] [BibTeX: guin2017obfuscation]
Journal Papers
  1. Y. Zhang, A. Jain, P. Cui, Z. Zhou, and U. Guin, "A Novel Topology-Guided Attack and Its Countermeasure Towards Secure Logic Locking," Journal of Cryptographic Engineering, pp. 1-14, 2020. [LINK] [PDF] [BibTeX: zhang2020novel]
  2. U. Guin, Z. Zhou, and A. Singh, “Robust Design-for-Security (DFS) Architecture for Enabling Trust in IC Manufacturing and Test," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 818-830, 2018. [LINK] [PDF] [BibTeX: guin2018robust]
  3. U. Guin, Q. Shi, D. Forte, and M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs," ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1-20, 2016. [LINK] [PDF] [BibTeX: guin2016fortis]
Conference Papers
  1. Y. Zhang, C. Tang, P. Li, and U. Guin , “CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs,” in Design Automation Conference (DAC), pp. 1-6, 2022. [PDF] [BibTeX: ]
  2. A. Jain, M. T. Rahman and U. Guin, “ATPG-Guided Fault Injection Attacks on Logic Locking,” in IEEE Physical Assurance and Inspection of Electronics (PAINE), pp. 1-6, 2020. [LINK] [PDF] [BibTeX: jain2020atpg]
  3. A. Jain, U. Guin, M. T. Rahman, N. Asadizanjani, D. Duvalsaint, and R. D. (Shawn) Blanton, “Special Session: Novel Attacks on Logic-Locking," in VLSI Test Symposium (VTS), pp. 1-10, 2020. [LINK] [PDF] [BibTeX: jain2020special]
  4. Y. Zhang, P. Cui, Z. Zhou, and U. Guin, “TGA: An Oracle-less and Topology-Guided Attack on Logic Locking," in Attacks and Solutions in Hardware Security (ASHES), pp. 75-83, 2019. [LINK] [PDF] [BibTeX: zhang2019tga]
  5. U. Guin, Z. Zhou, and A. D. Singh, “A Novel Design-for-Security (DFS) Architecture to Prevent Unauthorized IC Overproduction," IEEE VLSI Test Symposium (VTS), pp. 1-6, 2017. [LINK] [BibTeX: guin2017novel]