3DIC SoC Test Benchmarks

3DSC SoC Test Benchmarks

The 3DIC SOC Test Benchmarks is a set of benchmark circuits created with the purpose of evaluating SoC test scheduling methods. These benchmarks were built on previous benchmarks with the intent of providing information needed for power and thermal constrained test scheduling, which is not provided in previous benchmarks. These benchmarks are free to use for research purposes for testing of core-base SoCs, with the intent to save time for the researcher.

Motivation and Background

The first set of benchmarks created for the purpose of SoC Testing were the ITC'02 SoC Test Benchmarks. These benchmarks presented several SoCs with information required to evaluate hardware-constrained and pin-constrained test scheduling. However, these benchmarks lacked information required for other test scheduling environments. For instance, most of the individual ITC'02 Benchmarks lacked power information for tests, and those which had power information lacked detailed power traces. This made the ITC'02 Benchmarks inadequate for power-constrained test, or other forms of constrains that rely on power, such as temperature-constrained test. Studies in these fields were required to generate their own benchmarks for each of their studies.

The benchmarks provided here allow for a researcher to skip the process of creating benchmarks, therefore allowing more time and effort to be spent on research quality. Since these benchmarks are directly based off of the ITC'02 Benchmarks, the diversity of experiments in which these benchmark may be applied is large.

How to Use the Benchmarks?

Each benchmark consists of a stack of one or more dies, with each die being an SoC from the ITC'02 SoC Test Benchmarks. Each die is given a floor plan, which contains geometry information for each die. Each module has one or more tests, and each test is given a power trace file which gives power values for the test in a 400:1 ratio (one power trace value represents the average power of 400 clock cycles with a 120 MHz clock).

The use of these benchmarks is only limited to the desire of the researcher. The original intent of these benchmarks was for use in temperature-constrained test-scheduling. However, these benchmarks are also effective in power-constrained test-scheduling. If need be, one could use the benchmarks solely for the purposes of hardware-constrained test scheduling with added geometry information.

Although specific power traces, floor plans, and test clock information is given in the benchmarks, all these can be scaled to fit the needs of each researcher. Each die in these benchmarks has a die of area of 10 mm by 10 mm, and an average power density between 0.9 to 2.0 W/mm^2. However, these values may be outside the desired values for a particular study. The values in each benchmark can be easily scaled for this reason, and scaling is encouraged.

Benchmark Naming Scheme

The naming scheme used for the individual benchmarks is meant to represent the overall difficulty associated of the benchmark. A template for each benchmark naming is given below...

{# of dies in benchmark}_{Benchmark # with given number of dies}_{Relative number of tests per die}{Power difficulty}{Temperature difficulty}

The first part of the name is straightforward: how many dies or in the given benchmark. The second part is used distinguish between benchmarks that have the same number of dies. The third, fourth, and firth parts give a "high (H)", "medium (M)", or "low (L)" difficulty rating for the number of tests to schedule per die, the power density of the circuit, and the temperature impact of the tests when the benchmark is tested in a reasonable environment.

For example, the benchmark "2-7-HML" has two dies in it, and is the second benchmark with two dies in it. It has a large number of tests relative to the number of dies it has, it has fair power density, but its tests have a minimal temperature impact in a reasonable test environment.

These benchmark names are meant to help users decide which benchmarks to use based on their specific needs. However, power values and floor plans of benchmarks can be scaled to adjust the difficulty of the benchmarks as well.

Benchmark Format

Each benchmark is contained in its own folder, and all files pertaining to that benchmark are contained in its own folder. The format of the files were originally intended to be used in the Hotspot thermal simulator. The files types in each folder are as follows.

soc: original ITC'02 Benchmark file attached to each die (link is to ITC'02 website).
flp: floor plan file.
ptrace: power trace file, one for each test.
comp: example compatibility file, for use in studies where hardware compatibility is not the primary focus.

Benchmark Details

Below, a table of information on each benchmark is given. The highest temperature is the highest temperature achieved by a single test when run in a reasonable test environment (25 deg. C ambient temperature), and the power density is given in Watts per mm^2. For more details on the values shown here, as well as how they can be scaled to fit individual needs, see the benchmark format section.

Benchmark Name	# Dies	# Tests	Longest Test (power cycles)	Highest Temperature	Avg. Pow. Density
1-1-LLL	1	9	3049	29.07	1.09
1-2-MML	1	15	164	27.33	1.37
1-3-LLL	1	10	24	26.87	1.12
1-4-LLL	1	8	299	26.96	0.97
1-5-MHL	1	14	36	26.86	1.62
1-6-LML	1	4	842	28.97	1.57
1-7-LHL	1	4	5561	32.83	1.79
1-8-HHL	1	28	256	28.06	1.70
1-9-MML	1	19	1363	30.17	1.56
1-10-HML	1	32	287	27.83	14.33
1-11-HHL	1	31	13070	31.16	1.89
1-12-LHL	1	7	19353	34.5	1.89
2-1-MML	2	29	164	30.28	1.49
2-2-MLL	2	25	164	30.16	1.24
2-3-MML	2	24	36	26.87	1.37
2-4-LML	2	12	842	30.41	1.34
2-5-HHL	2	42	256	27.65	1.66
2-6-MMM	2	23	1363	36.37	1.45
2-7-HML	2	60	287	32.7	1.59
2-8-MHM	2	35	1307	44.28	1.84
2-9-HHM	2	63	13070	42.92	1.66
2-10-MHH	2	38	19353	46.62	1.89
3-1-MML	3	39	164	30.29	1.37
3-2-MMM	3	33	842	39.81	1.44
3-3-LML	3	22	5561	34.03	1.58
3-4-HMM	3	79	1363	37.53	1.56
3-5-MHH	3	54	19353	58.53	1.72
3-6-HHM	3	70	19353	41.95	1.74
4-1-MLL	4	47	299	29.1	1.27
4-2-HHH	4	83	5561	65.7	1.62
4-3-HHH	4	89	19353	48.23	1.69
5-1-MHH	5	64	19353	52.77	1.63

Benchmark Files

All files are included in a single tar.gz file, bench.tar.gz. Although the compressed file is 3MB in size, it is recommended that only necessary benchmarks be extracted since the total size of all extracted benchmarks is 186MB.

Citing the Benchmarks

The benchmarks provided in this site are free to use for any purpose. However, we ask that if you do use these benchmarks that you cite one of the following papers introducing the benchmarks. Also, since these benchmarks are heavly based on the ITC'02 Benchmarks, we ask that users of these benchmarks also cite the ITC'02 given below.

No papers are available yet. Please cite the website instead.

ITC'02 Benchmarks Paper:

[1] E. J. Marinissen, V. Iyengar, and K. Chakrabarty, "A set of benchmarks for modular testing of SOCs," in Proceedings. International Test Conference, 2002, pp. 519-528.

Contact

All questions, comments, or concerns regarding the benchmark can be directed to Spencer Millican at millican (at) auburn (dot) edu. Feel free to point out errors in the benchmarks or the website.

Last Updated: Nov 10, 2021