3DIC SoC Test Benchmarks (Floor Plans)
3DSIC SOC Test Benchmarks (Floor Plans)
The format for floor plan files for each die is based on the floor plan file format used in the Hotspot thermal simulator. In each floor plan file, each line corresponds to a single module. The exact format is as follows, with all dimensions being in meters.
Module_name module_width module_height bottom_left bottom_y
Embedded Modules
Since the original ITC'02 Benchmarks consisted of embedded modules, embedded modules are also included in this set of benchmarks. The naming convention for a standard module is...(DIE_NAME)M(MODULE_NUMBER)t(TEST_NUMBER).
For an embedded module, the format is
(DIE_NAME)M(MODULE_NUMBER)_(EMBEDDED_NUMBER)t(TEST_NUMBER).
For the purposes of testing, a test for a given module is presumed to dissipate power in all embedded modules, and applying tests for tests for embedded modules is impossible while the parent module is being tested.
Scaling
Each die in each benchmark has a floor plan area of 10 by 10 mm^2. Although this is a fair size for modern integrated circuits, this floor plan area may not fit the need of every research project. Some projects may desire smaller floor plan areas, while other may required several different floor plan areas.Researchers are encouraged to scale the dies to the sizes required by their study. Doing so is a simple process of multiplying/dividing the values of each floor plan file by a given constant.
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Last Updated:
Nov 10, 2021
