Contact Information:
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Spencer Millican |
Bio Sketch
Spencer Millican has been an Assistant Professor with the Department of Electrical and Computer Engineering at Auburn University since Fall of 2017. His research and teaching expertise is in the area of computer engineering, VLSI design, electronic design automation (EDA), design-for-test (DFT), hardware security, and intellectual property (IP) protection.
Prof. Millican was previously a member of the staff at the IBM development and manufacturing facility in Rochester, MN from 2015 - 2017. While at IBM, he designed circuit testability hardware and developed solutions to test circuits under 14nm constraints. He developed and deployed built-in self-test (BIST) circuitry for IBM P9 and Z processors. His research interests at IBM were increasing the effectiveness and quality of random tests, especially for the constraints of sub-14nm designs.
Prof. Millican graduated with his Ph.D. from the University of Wisconsin - Madison in 2015 under the guidance of Prof. Kewal Saluja and Prof. Parameswaran Ramanathan. His thesis was on the optimization of system-on-chip (SoC) test schedules under power and temperature constraints both with and without dynamic voltage and frequency scaling (DVFS) and 3D stacked integrated circuit (3DIC/3DSIC) architectures. He also simultaneously pursued the encryption of IP cores for safe distribution and simulation.
VLSI Test Lab
The current interests of the VLSI Test Lab include:
- Encryption of intellectual property digital designs for simulation and verification.
- Random resistant fault detection.
- Low-power and low-temperature test.
- Optimization of test economics.
- Modeling and detection of faults in sub-14nm technology.
VLSI Test Lab's Code Repository
The VLSI Test Lab maintains a repository for all source code used to create artifacts for publication. The code is open-source under the MIT license, and users of the code are encouraged to cite its location and related publications if used.
Questions regarding the code should be directed to millican@auburn.edu, which will be forwarded to appropriate developers.
Students
Gavin McCormick (Ph.D. 202X)
Yang Sun (M.S. 2018, Ph.D. 2021)
Soham Roy (Ph.D. 2021)
Joshua Immanuel (M.S. 2029)
Ayokunle Fadamiro (M.S. 2020)
Prospective Students
I am available to advise any students who are on campus.
Feel free to ask any additional questions.
Recent Publications (updated Sept. 16, 2022)
Sun, Yang and Spencer K. Millican. “Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test-point Insertion.” Journal of Electronic Testing 38, no. 3 (August 4, 2022).
Roy, Soham, Spencer K. Millican and Vishwani D. Agrawal. “Multi-heuristic Machine Intelligence Guidance in Automatica Test Pattern Generation.” In Proc. IEEE 13th Microelectronics Design & Test Symp. (MDTS), 1-6. Albany, NY, USA, July 2022.
Spencer Millican, Yang Sun, Soham Roy and Vishwani D. Agrawal. System and method for optimizing fault coverage based on optimized test point insertion determination for logical circuits. US Patent Application 17/226,950, Filed April 09, 2021.
Millican, Spencer and SueAnne Griffith. “Work-in-Progress: A Study of Transistor Degradation in Cyber-Physical System Control Devices.” In Proc. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 37–38. Austin, TX, USA, Oct. 2021.
Fadamiro, Ayokunle, Pouyan Rezaie, Spencer Millican, and Christopher B. Harris. “A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories.” In Proc. IEEE International Symposium on Multiple-Valued Logic (ISMVL), 166–71. Nur-sultan, Kazakhstan, May 2021.
Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Principal Component Analysis in Machine Intelligence-Based Test Generation.” In Proc. IEEE Microelectronics Deign & Test Symposium (MDTS). Albany, NY, USA, May 2021.
Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Unsupervised Learning in Test Generation for Digital Integrated Circuits.” In Proc. IEEE European Test Symposium (ETS). Bruges, Belgium, May 2021.
Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Special Session – Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits.” In Proc. IEEE VLSI Test Symposium (VTS). San Diego, CA, USA, April 2021.
Roy, Soham, Spencer K. Millican, and Vishwani D. Agrawal. “Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator.” In Proc. IEEE International Conference on VLSI Design (VLSI-D), 316–21. Guwahati, India, Feb. 2021.
Fadamiro, Ayokunle, Pouyan Rezaie, Christopher Harris, and Spencer Millican. “Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-Gate Memories and Voltage Division.” In Proc. ACM/SIGDA Intl. Symp. FPGAs, 226. Virtual Event, Feb. 2021.
Soham Roy, Spencer K. Millican, and Vishwani D. Agrawal. “Machine Intelligence for Efficient Test Pattern Generation.” In 51st IEEE International Test Conference (ITC). Nov. 2020.
Joshua Immanuel and Spencer K. Millican. “Calculating Signal Controllability using Neural Networks: Improvements to Testability Analysis and Test Point Insertion.” In 29th IEEE North Atlantic Test Workshop (NATW). June 17, 2020.
Ayokunle Fadamiro, Pouyan Rezaie, Christopher B. Harris, and Spencer K. Millican. “A Quaternary FPGA Architecture Using Floating Gate Memories.” In IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Fayetteville, AR, 2020.
Yang Sun, Spencer K. Millican, and Vishwani D. Agrawal. “Special Session: Survey of Test Point Insertion for Logic Built-in Self-test.” In IEEE 38th VLSI Test Symposium (VTS). San Diego, CA, 2019.
Roy, Soham, Brandon Stiene, Spencer K. Millican, and Vishwani D. Agrawal. “Improved Pseudo-Random Fault Coverage Through Inversions: A Study on Test Point Architectures.” Journal of Electronic Testing 36, no. 1 (February 3, 2020): 123–33.
Spencer K. Millican, Yang Sun, Soham Roy, and Vishwani D. Agrawal. “Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training.” In 28th IEEE Asian Test Symposium (ATS). Kolkata, India, 2019.
Sankaran Menon, Chinna Prudvi, Rolf Kuehnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra, and Ashish Gupta. “Techniques for Debug of Low Power SoCs.” In 20th International Workshop on Microprocessor/SoC Test, Security & Verification (MTV19). Austin, TX, 2019.
Spencer K. Millican, Yang Sun, Soham Roy, and Vishwani D. Agrawal. “Applying Artificial Neural Networks to Test-point Insertion: Delay Fault Coverage and Training Circuit Generation.” In Proc. 50th International Test Conference (ITC). Washington, DC, 2019.
Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, and Vishwani D. Agrawal. “Special Session: Delay Fault Testing-Present and Future.” In IEEE 37th VLSI Test Symposium (VTS). Monterey, CA, 2019.
Soham Roy, Brandon Stiene, Spencer K. Millican, and Vishwani D. Agrawal. “Improved Random Pattern Delay Fault Coverage Using Inversion Test Points.” In IEEE 28th North Atlantic Test Workshop (NATW). Essex, VT, 2019.
Yang Sun and Spencer K. Millican. “Test Point Insertion Using Artificial Neural Networks.” In IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Miami, FL, 2019.
Ashish Gupta, Pandy Kalimuthu, Rolf Kuhnis, Sankaran Menon, Spencer K. Millican, Preeti Ranjan Panda, Priyadarsan Patra, Eric Rentschler, Sukhbinder Singh Takhar, and Gaurav Verma. “Debug Infrastructure for System-on-chips.” IEEE Silicon Valley Debug Technical Committee (SVDTC), 2019. [Online]. Available:
https://sites.google.com/a/ieee-ceda.com/svdtc/activities/svdtcsocdebugwhitepaperreleaseddec2018
Millican, Spencer, “An Open Source Code Base for Digital Circuit Analysis, Simulation, and Modification,” in 1st Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, 2018.
Millican, Spencer, and Kewal Saluja, “System-on-Chip Scheduling Benchmarks for New Technologies,” in 1st Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, 2018.
Millican, Spencer, and Kewal Saluja, “TESTCAD: A Verified Education Toolset for a Course in Digital Testing,” in 1st Workshop on Open-Source EDA Technology (WOSET), San Diego, CA, 2018.
S. K. Millican, P. Ramanathan, and K. K. Saluja, “CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities,” in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp. 92–97. (Awarded “Best Paper”)
S. K. Millican and K. K. Saluja, “Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints,” in 2015 28th International Conference on VLSI Design, 2015, pp. 487–492.
S. K. Millican and K. K. Saluja, “Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits,” in IEEE 21st Asian Test Symposium, 2012, pp. 37–42.
S. K. Millican and K. K. Saluja, “Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling,” J. Electron. Test., vol. 30, no. 5, pp. 569–580, Sep. 2014.
S. K. Millican and K. K. Saluja, “Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling,” in 22nd AsianTest Symposium (ATS), 2013, pp. 165–170.
S. K. Millican and K. K. Saluja, “A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits,” in 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014, pp. 20–25.