The new cell-aware IC test methodology has received much publicity recently because of its success in screening significant defectivity missed by traditional stuck-at and transition delay fault (TDF) testing. For example, Mentor/AMD reported at ITC 2012 that cell aware tests detected an additional 885 defective parts per million (DPM) test escapes in a 32 nm notebook processor part, already extensively tested with conventional high coverage stuck-at and TDF tests. Importantly, most of these test escapes were observed to cause failure in actual system application, pointing to a potentially serious field reliability problem. IC suppliers targeting “zero defect” automotive applications have already integrated these new fault models into their test flow, despite the significant cost increase from a near doubling of test pattern counts. However, even the new tests appear unable to detect many faulty parts in complex low yielding microprocessor and smartphone SOCs.  Today, these applications are increasing relying on expensive system level tests (SLTs) as a final screen for defective devices. Mobile phone SOCs, for example, are temporarily mounted on specially designed, reusable, phone boards, and a broad range of functional applications are run as a final check of full functionality. 

This presentation will review the state-of-the-art in fault model based structural testing, including cell aware tests, to understand the defects types that likely remain undetected by conventional scan testing and therefore necessitate additional system level tests. Since applying SLTs on all manufactured parts can be extremely expensive, a key objective for industry is to minimize the use of such tests. SLTs are often indispensable early in production when yields are low; the goal typically is to reduce use of these tests as the process matures and stabilizes. However, this is proving quite challenging. We will discuss the needed improvements in structural test methods that may help mitigate this problem.