VLSI Testing Course by
Michael L. Bushnell
and
Vishwani D. Agrawal
Auburn University:
ELEC7250-001 (Spring 2006) VLSI Testing
,
FINAL GRADING TABLE
ELEC7250-001 (Spring 2005) VLSI Testing
,
FINAL GRADING TABLE
/
GRAPH
ELEC 7250 (Spring 2004): VLSI Testing
,
Class Assignments
,
Course Bulletin (Finals and Grades)
Rutgers University: VLSI Testing (Spring 2002):
Syllabus
/
Homework Assignments
Class Projects
/ Rutgers Modeling Language (rutmod) User's Manual (14 pages)
pdf
Text-Book, Solution Manual, etc.
Full-Semester Course:
Original sequence -- 1 through 31
Alternative sequence -- 1 through 7,
8alt
,
9alt
, 10,
11alt
through
22alt
(shortened for one-semester course)
Lecture 1: Introduction (powerpoint, 16 slides)
Lecture 2: VLSI Test Process and Equipment (powerpoint, 43 slides)
Lecture 3: Test Economics (powerpoint, 16 slides)
Lecture 4: Yield Analysis & Product Quality (powerpoint, 15 slides)
Lecture 5: Fault Modeling (powerpoint, 18 slides)
Lecture 6: Logic Simulation (powerpoint, 15 slides)
Lecture 7: Fault Simulation (powerpoint, 20 slides)
Lecture 8: Testability Measures (powerpoint, 36 slides)
Lecture 8alt: Testability Measures (powerpoint 27 slides)
Lecture 9: Combinational ATPG Basics (powerpoint, 26 slides)
Lecture 9alt: Combinational ATPG (powerpoint, 37 slides)
Lecture 10: Combinational ATPG and Logic Redundancy (powerpoint, 9 slides)
Lecture 11: Major Combinational ATPG Algorithms (powerpoint, 71 slides)
Lecture 11alt: Advances in Combinational ATPG Algorithms (powerpoint, 23 slides)
Lecture 12: Advanced Combinational ATPG Algorithms (powerpoint, 57 slides)
Lecture 13
(12alt)
: Seq. Circuit ATPG - Time-Frame Expansion (powerpoint, 24 slides)
Lecture 14
(13alt)
: Seq. Circuit ATPG - Simulation-Based Methods (powerpoint, 25 slides)
Lecture 15: Memory Test (powerpoint, 65 slides)
Lecture 14alt: Memory Test (powerpoint, 27 slides, alternative Lecture 15)
Lecture 16: Pattern Sensitive and Electrical Memory Test (powerpoint, 33 slides)
Lecture 15alt: Memory NPSF and Parametric Test (powerpoint, 25 slides, alternative Lecture 16)
Lecture 17: Analog Circuit Test - A/D and D/A Converters (powerpoint, 34 slides)
Lecture 16alt: Analog Test and IEEE 1149.4 Standard (powerpoint, 26 slides, alternative to Lectures 17, 18, 19 and 30)
Lecture 18: DSP-Based Analog Circuit Testing (powerpoint, 57 slides)
Lecture 19: Fault Model Based Structural Analog Testing (powerpoint, 22 slides)
Lecture 20
(17alt)
: Delay Test (powerpoint, 25 slides)
Lecture 21: IDDQ Current Testing (powerpoint, 39 slides)
Lecture 22: Delta-IDDQ Testing and Built-In Current Testing (powerpoint, 18 slides)
Lecture 18alt: IDDQ Testing (powerpoint, 24 slides, alternative to Lectures 21 and 22)
Lecture 23
(19alt)
: Design for Testability - Full Scan (powerpoint, 22 slides)
Lecture 24: Design for Test. - Partial Scan & Scan Variations (powerpoint, 20 slides)
Lecture 20alt: DFT - Partial, Random-Access and Boundary Scan (powerpoint, 26 slides, alternative to Lectures 24, 28 and 29)
Lecture 25: BIST Pattern Generation & Response Compaction (powerpoint, 59 slides)
Lecture 26: BIST Architectures (powerpoint, 24 slides)
Lecture 27: Memory and Delay Fault BIST (powerpoint, 24 slides)
Lecture 21alt: BIST - Built-In Self-Test (powerpoint, 28 slides, alternative to Lectures 25, 26 and 27)
Lecture 28: IEEE 1149.1 Boundary Scan Standard (powerpoint, 32 slides)
Lecture 29: Advanced Boundary Scan and BSDL (powerpoint, 21 slides)
Lecture 30: IEEE 1149.4 Analog Bus Standard (powerpoint, 34 slides)
Lecture 31
(22alt)
: System Test (powerpoint, 22 slides)
Short Courses:
Two-Day Course: Testing Analog and Digital Products, Penang, July 12-13, 2005
Four-Day Course: Design for Testability - Theory and Practice, Bangalore, July 27-30, 2005
Three-Day Course: Design for Testability - Theory and Practice, New Delhi, Dec 15-17, 2005
Three-Day Course: Design for Testability - Theory and Practice, Hyderabad, July 27-39, 2006
Schedule
Day1
Day2
Day3
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