Three-Day Seminar on Design for Testability Theory and Practice
New Delhi, India, December 15-17, 2005
Course Schedule

Instructors:
Vishwani D. Agrawal, James J. Danaher Professor of ECE, Auburn University
Dr. C. P. Ravikumar, Texas Instruments, Bangalore

Lecture 1: Introduction, Dec 15, 2005
Lecture 2: Yield and Quality, Dec 15, 2005
Lecture 3: Fault Modeling, Dec 15, 2005
Lecture 4a: Logic Simulation, Dec 15, 2005
Lecture 4b: Fault Simulation, Dec 15, 2005
Lecture 5: Testability Measures, Dec 15, 2005
Lecture 6: Combinational ATPG, Dec 15, 2005

Test 1

Lecture 7: Sequential ATPG, Dec 16, 2005
Lecture 8: Memory Test, Dec 16, 2005
Lecture 9: Analog Test, Dec 16, 2005
Lecture 10: DFT and Scan, Dec 16, 2005
Lecture11: BIST, Dec 16, 2005
Lecture 12: System Diagnosis, Dec 16, 2005

Test 2

Lecture 13: Test Compression Techniques, Dec 17, 2005
Lecture 14: At-Speed Testing Techniques for SoC, Dec 17, 2005
Lecture 15: Signal Integrity Issues in Test, Dec 17, 2005
Lecture 16: Power Issues in Test, Dec 17, 2005