Doctoral, Master's and Honors Theses Supervised or served on Committee (Click on name for present email address):

Kaniz Fatema Mishty (Apple, CA), PhD, Auburn, Oct 24, 2024 (Mehdi Sadi, Advisor), AI-aided System and Design Technology Co-optimization Methodology Towards Designing Energy-efficient and High performance AI Accelerator
Yadi Zhong (AU-ECE Asst. Prof.), PhD, Auburn, May 4, 2024 (Ujjwal Guin, Advisor), When Alice meets the “Hardware” Bob — Attacks and Solutions in the Digital World
Yang Sun PhD, Auburn, Dec 11, 2021 (Spencer Millican, Advisor), Novel Test Point Insertion Applications in LBIST
Ziqi Zhou (Cadence, Austin, TX), PhD, Auburn, Aug 7, 2021 (Ujjwal Guin, Advisor), Novel Approaches for Microelectronics Security and Test Defense
Soham Roy (Intel, Santa Clara, CA), PhD, Auburn, Aug 7, 2021, Toward Zero Backtracks in Test Pattern Search Algorithms with Machine Learning Defense
Francy John Akkara (SkyWorks Solutions Inc, Newbury, CA), PhD, Auburn, May 1, 2021 (Sa'd Hamasha, Advisor), Thermal Cycling Reliability of Doped SnAgCu Solder Alloys after Long-Term Aging Defense
Murali Venkatasubramanian (Intel, Hillsboro, OR), PhD, Auburn, Nov 4, 2016, Failure Evasion: Statistically Solving the NP Complete Problem of Testing Difficult-to-Detect Faults Defense
Harshit Goyal, MS, Auburn, Aug 6, 2016, Characterizing Processors for Time and Energy Optimization Defense
Samuel Sungil Kim (PhD, MIT, April 2021, Fish & Richardson, NYC), BS Honors, Auburn, May 8, 2016, Subthreshold Circuit Design and Optimization
George G. Conover, MS, Auburn, Dec 12, 2015, Alternative Timing in Digital Logic Defense
Xiaolu Shi, MS, Auburn, June 8, 2015, Diagnostic Test Generation for Transition Delay Faults Using Two-Timeframe ATPG Model Defense
Heng Zhao (Walmart Technology, Dallas, TX), MEE, Auburn, June 5, 2015, Test Programming an ATE for Diagnosis Defense
Zeshi Luo (Microsoft, China), MS, Auburn, May 20, 2015, Diagnostic Test Generation for Path Delay Faults in a Scan Circuit Defense
Baohu Li (nVIDIA, CA), PhD, Auburn, Apr 15, 2015, Digital Testing with Multivalued Logic Signals Defense
Huiting Zhang (Amazon Lab126, CA), MEE, Auburn, Apr 9, 2015, NATW 2015 Paper: SoC TAM Design to Minimize Test Application Time Defense
Hejia Liu (Broadcom, San Diego), MEE, Auburn, Apr 8, 2015, ATS 2015 Paper: Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key Defense
Bei Zhang (Apple, Cupertino, CA), PhD, Auburn, Sep 30, 2014, Pre-bond TSV Test Optimization and Stacking Yield Improvement for 3D ICs Defense
Jia Yao (Qualcomm, Austin TX), PhD, Auburn, May 19, 2014, Dual-Threshold Voltage Design of Sub-Threshold Circuits Defense
Sindhu Gunasekar (Google, CA), MS, Auburn, Apr 2, 2014, Finding Optimum Clock Frequencies for Aperiodic Test Defense
Vijay Sheshadri (Intel, OR), PhD, Auburn, Feb 26, 2014, Power-Aware System-on-Chip Test Optimization through Frequency and Voltage Scaling Defense
Praveen Venkataramani (Advantest, CA), PhD, Auburn, Nov 8, 2013, Reducing ATE Test Time by Voltage and Frequency Scaling Defense
Karthik Naishathrala Jayaraman (Concept2Silicon, Bangalore), MS, Auburn, Oct 2, 2013, DVF4: A Dual Vth Feedback Based 4-Transistor Level Converter Defense
Rathan Raj, MEE, Auburn, Oct 1, 2013, Using Cycle Efficiency as a System Designer Metric to Characterize an Embedded DSP and Compare Hard Core vs. Soft Core Defense
Sachin Chandran (Intel, OR), MEE, Auburn, Sep 25, 2013, A Survey of Clock Distribution Techniques Including Optical and RF Networks Defense
Mustafa Shihab (Intel, Santa Clara, CA), MS, Auburn, June 28, 2013, PhD 2021 (UTD), A High-Voltage On-Chip Power Distribution Network (MS Thesis) Defense
Farah N. Taher (Raytheon, Richardson, TX), MS, Auburn, June 21, 2013, PhD 2019 (UTD), A Low-Power Analog Bus for On-Chip Communication (MS Thesis) Defense
Suraj Sindia (Intel, OR), PhD, Auburn, June 8, 2013, High Sensitivity Signatures for Test and Diagnosis of Analog, Mixed-Signal and Radio-Frequency Circuits Defense
Chidambaram Alagappan (Advantest, OR), MS, Auburn, May 4, 2013, Dictionary-Less Defect Diagnosis as Real or Surrogate Single Stuck-At Faults, Defense
Aditi Shinde (AMD, Boston Area, MA), MEE, Auburn, Dec 8, 2012, Managing Performance and Efficiency of a Processor, Defense
Yu Zhang (nVIDIA, CA), PhD, Auburn, Aug 4, 2012, Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults, Defense
Xi Li (Invexer Technology, VA), MEE, Auburn, May 2012, Survey of Wireless Network-on-Chip Systems Defense
Farhana Rashid (Intel, Austin, TX), MS, Auburn, May 2012, Controlled Transition Density Based Power Constrained Scan-BIST with Reduced Test Time Defense
Lixing Zhao (Qualcomm, San Diego, CA), MS, Auburn, December 2011, Net Diagnosis Using Stuck-at and Transition Fault Models Defense
Mridula Allani (Intel, Santa Clara, CA), MS, Auburn, December 2011, Polynomial-Time Algorithms for Designing Dual-Voltage Energy Efficient Circuits Defense
Kyungseok Kim (Qualcomm, NC), PhD, Auburn, May 2011, Ultra Low Power CMOS Design, Defense
Wei Jiang (GlobalFoundries, Essex Junction, VT), PhD, Auburn, May 2011, Built-In Self-Test and Calibration of Mixed-Signal Devices, Defense
Muralidharan Venkatasubramanian (Intel, Hillsboro, OR), MS, Auburn, May 2011, Energy Efficiency and Process Variation Tolerance of 45nm Bulk and High-k CMOS Devices, Defense
Rakshith Thambehalli Venkatesh (nVIDIA, CA), MS, Auburn, May 2011, Secondary Bus Performance in Reducing Cache Writeback Latency
Priyadharshini Shanmugasundaram (Apple, Austin, TX), MS, Auburn, December 2010, Test Time Optimization in Scan Circuits, Defense
Manish Kulkarni (Nvidia GeForce, Santa Clara, CA), MS, Auburn, December 2010, Energy Source Lifetime Optimization for a Digital System through Power Management, Defense
Nitin Yogi (nVIDIA, CA), PhD, Auburn, August 2009, Spectral Methods for Testing of Digital Circuits, Defense
Chaitanya Bandi (Intel, CA), MEE, Auburn, August 2009, Fully Configurable Hierarchical Transaction Level Verifier for Functional Verification, Defense
Mohammed Ashfaq Shukoor (Qualcomm, Austin, TX), MS, Auburn, May 2009, Fault Detection and Diagnostic Test Set Minimization, Defense
Khushboo Sheth (Intel, Santa Clara, CA), MS, Auburn, December 2008, A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management, Defense
Jins D. Alexander (Texas Instruments, Dallas, TX), MS, Auburn, December 2008, Simulation Based Power Estimation for Digital CMOS Technologies, Defense
Hillary Grimes (Continental Controls Corp., CA), MS, Auburn, August 2008, Reconvergent Fanout Analysis of Bounded Gate Delay Faults, Defense
Fan Wang (tangarine.com), MS, Auburn, May 2008, Soft Error Rate Determination for Nanometer CMOS VLSI Circuits, Defense
Christopher Rose, BS Honors, Auburn, June 2007, Active Voice Control: An Implementation of Active Noise Control for Canceling Speech
Yuanlin Lu (Intel, CA), PhD, Auburn, August 2007, Power and Performance Optimization of Static CMOS Circuits with Process Variation, Defense
Kalyana R. Kantipudi (Altera, CA), MS, Auburn, May 2007, Minimizing N-Detect Tests for Combinational Circuits, Defense
Alok S. Doshi (Altera, CA), MS, Auburn, May 2006, Independence Fault Collapsing and Concurrent Test Generation, Defense
Fei Hu (Qualcomm, San Diego, CA), PhD, Auburn, May 2006, Process-Variation-Resistant Dynamic Power Optimization for VLSI Circuits, Defense
Anand Mudlapur (Micron, Folsom, CA, since 2018), MS, Auburn, May 2006, Practically Realizing Random Access Scan, Defense
Subhashis Majumder (Heritage Inst. Tech., India), PhD, Jadavpur, Oct 2005, Studies in Layout-driven Routing, Thermal Problems and Delay Fault Classification for VLSI Physical Design
Raja Kiran Kumar Reddy Sandireddy (Dell EMC, Santa Clara, CA), MS, Auburn, May 2005, Hierarchical Fault Collapsing for Logic Circuits, Defense
Siri Uppalapati (Intel, CA), MS, Rutgers, October 2004, Low Power Design of Standard Cell Digital VLSI Circuits, Defense
Tezaswi Raja (nVIDIA, CA), PhD, Rutgers, May 2004, Minimum Dynamic Power CMOS Design with Variable Input Delay Logic, Defense
Kunal K. Dave (Apple), MS, Rutgers, May 2004, Using Contrapositive Rule to Enhance the Implication Graphs of Logic Circuits, Defense
Vishal J. Mehta (nVIDIA, CA), MS, Rutgers, May 2003, Redundancy Identification in Logic Circuits using Extended Implication Graph and Stem Unobservability Theorems
Lan Rao (Sun Microsystems), PhD, Rutgers, 2003, Graphical CMOS IDDQ Testing Signatures Based on Data Mining.
Yong C. Kim (AFRL/RYWA, Wright-Patterson AFB, OH), PhD, Wisconsin, 2002, Combinational Test Generation for Sequential Circuits.
Tezaswi Raja, MS, Rutgers, March 2002, A Reduced Constraint Set Linear Program for Low-Power Design of Digital Circuit
Vivek Gaur (Synopsys, CA), MS, Rutgers, January 2002, A New Transitive Closure Algorithm to Identify Redundancies in Logic Circuits.
Pradip A. Thaker (Marvell Technology, Bengaluru, India), PhD, GWU, May 2000, Register-Transfer Level Fault Modeling and Test Evaluation Technique for VLSI Circuits
Carlos G. Parodi, MS, Rutgers, January 1999, Exact Non-Enumerative Path-Delay Fault Simulation of Sequential Circuits.
Keerthi Heragu (Texas Instruments, Dallas, TX), PhD, Illinois, November 1997, New Techniques to Verify Timing Correctness of Integrated Circuits.
Ananta K. Majhi (NXP, Holland), PhD, IISc, 1996, Algorithms for Test Generation and Fault Simulation of Path-Delay Faults in Logic Circuits
Marwan A. Gharaybeh (Samsung, CA), PhD, Rutgers, October 1996, Testing for Timing Correctness of High-Speed VLSI Circuits.
Qing Lin (Broadcom, CA), MS, Rutgers, 1996, Efficient Techniques for a Transitive-Closure Based Test Generation Algorithm.
Soumitra Bose (NJ), PhD, CMU, December 1995, Testing for Path Delay Faults in Synchronous Sequential Circuits.
James Sienicki (NJ), PhD, Rutgers, October 1995, Algorithms and Models for Distributed Test Generation.
Keerthi Heragu, MS, Rutgers, May 1994, Approximate and Statistical Methods to Compute Delay Fault Coverage.
Srinivas Komar (Mentor, CA), PhD, IISc, 1994
Suman Kanjilal, PhD, Rutgers, 1994, Synthesis for Testability Using Test Functions.
Tapan J. Chakraborty (Qualcomm, CA), PhD, Rutgers, October 1993, Delay Fault Test-Pattern Generation for Random Logic State Machines.
D. V. Das (India), PhD, Nebraska, 1992
Srimat T. Chakradhar (NEC Labs, NJ), PhD, Rutgers, May 1990, Neural Network Models for Test-Pattern Generation.
Hassan A. Farhat (U. Nebraska, Omaha), PhD, Nebraska, 1988
Kwang-Ting (Tim) Cheng (UCSB, CA), PhD, UC-Berkeley, 1988, A Simulation-Based Directed-Search Method for Test Vector Generation.
Vishwani D. Agrawal (Auburn U, AL), PhD, UIUC, 1971, Mutual Coupling in Phased Arrays of Randomly Spaced Antennas.

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