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Journal Papers (Accepted)
| K. Mishty and M. Sadi, "System and Design Technology Co-optimization of SOT-MRAM for High-Performance AI Accelerator Memory System", IEEE Transactions on Computers (TC) , 2022. | |
| K. Mishty and M. Sadi, "Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM", IEEE Transactions on Very Large Scale Integration Systems (TVLSI) , 2021, [LINK]. | |
| M. Sadi and U. Guin, "Yield Loss Reduction and Test of AI and Deep Learning Accelerators", IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD) , 2021, [LINK]. | |
| M. Alam, A. Nahiyan, M. Sadi, D. Forte, and M. Tehranipoor, "Soft-HaT: Software-based Silicon Reprogramming for Hardware Trojan Implementation", ACM Transactions on Design Automation of Electronic Systems (TODAES) , 2020. [PDF] | |
| M. Sadi, G. Contreras, J. Chen, L. Winemberg and M. Tehranipoor, "Design of Reliable SoCs With BIST Hardware and Machine Learning", IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2017 [PDF] | |
| M. Sadi, S. Kannan, L. Winemberg and M Tehranipoor, "SoC speed binning using machine learning and on-chip slack sensors", IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD) , 2019, [LINK]. | |
| M. Sadi, and M. Tehranipoor "Design of a network of digital sensor macros for extracting power supply noise profile in SoCs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2015. [LINK]. | |
| X. Wang, P. Jiao, M. Sadi, L. Winemberg, M Tehranipoor, "TRO: an on-chip ring oscillator-Based GHZ transient IR-drop monitor", IEEE Transactions on Computer-Aided Design of Integrated Circuits , 2016. [LINK] |
Conference Papers
| S. Kundu, K. Basu, M. Sadi, T. Titirsha, S. Song,, A. Das, U. Guin. et. al., “Special Session: Reliability Analysis for ML/AI Hardware”, in VLSI Test Symposium (VTS), 2021 [LINK]. | |
| M. Sadi et. al., “A Framework for Benchmarking the Impact of Transistor and Interconnect Technology on Designs”, in Intel Design and Test Technology Conference (DTTC), Portlan, OR, 2019 . | |
| A. Nahiyan, M. Sadi, R. Vittal, G. Contreras, D. Forte, and M. Tehranipoor, “Hardware trojan detection through information flow security verification”, in IEEE International Test Conference (ITC), 2017 [LINK]. | |
| M. Sadi, S. Kannan, L. England, and M. Tehranipoor, “Design of a digital IP for 3D-IC die-to-die clock synchronization”, in IEEE International Symposium on Circuits and Systems (ISCAS) , 2017 [LINK]. | |
| M. Sadi, G. Contreras, D. Tran, J. Chen, L. Winemberg, M. Tehranipoor, “BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning”, in IEEE International Test Conference (ITC) , 2016 [LINK]. | |
| S. Kannan, M. Sadi, and L. England, “Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors”, in IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , 2016 [LINK]. | |
| L. Yu, X Wang, L. Winemberg, M. Sadi, M Tehranipoor , “An efficient all-digital IR-Drop Alarmer for DVFS-based SoC”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2016 [LINK] | |
| M. Sadi, M Tehranipoor, X Wang, and LR Winemberg, “Speed binning using machine learning and on-chip slack sensors”, in Great Lakes Symposium on VLSI (GLSVLSI) , 2015 [LINK]. | |
| M Sadi, L Winemberg, and M Tehranipoor, “A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs”, in IEEE VLSI Test Symposium (VTS), 2015 [LINK][PDF]. |
Patents
S. Kannan, L. England, and M. Sadi,
"Method, apparatus and system for voltage compensation in a semiconductor wafer", 2018, US 10,069,490 B2. [LINK ]
S. Kannan, L. England, and M. Sadi,
"Latency compensation network using timing slack sensors", 2017, US 9,716.487 B1 . [LINK ]