Assistant professor in electrical and computer engineering revolutionizes chiplet designs, earns NSF CAREER Award
Published: Feb 3, 2025 10:35 AM
By Joe McAdory
Traditional monolithic chip designs in everyday devices such as cellphones and laptops face significant limitations due to high manufacturing costs and size constraints.
Mehdi Sadi, an assistant professor in electrical and computer engineering (ECE), is addressing these challenges posed by modern artificial intelligence (AI) workloads, which demand large silicon areas for optimal performance.
His project, “Optimizing the Next Frontiers of Chiplet-based Designs in Advanced Packaging,” develops AI/machine learning-assisted co-design methodologies to enhance the power, performance, reliability and cost-efficiency of next-generation AI hardware using multi-tier chiplet architectures, while also creating educational resources and fostering a skilled workforce.
The result: smaller chips with greater performance and energy efficiency… at a reduced cost.
For his work, Sadi earned a National Science Foundation (NSF) Faculty Early CAREER Award, drawing $512,000 throughout five years for his research.
As described by the NSF, the Faculty Early Career Development (CAREER) Program offers the foundation's most prestigious awards in support of early-career faculty who have the potential to serve as academic role models in research and education and to lead advances in the mission of their department or organization.
“As always, CAREER awards are very competitive,” said Sadi. “The research tasks must address an important and timely problem worthy of long-term research investment and effort. The proposed solutions need to be novel and innovative. Recently, semiconductors and computer chip technology have become critical U.S. national interests. My research is at the intersection of Al/deep learning-based optimization and semiconductor technology for next-generation AI hardware design. Receiving the prestigious CAREER award is a testament to the significance of my research.”
Sadi also earned a two-year, $174,923 NSF grant in 2022 for his project, “Design and System Technology Co-optimization Towards Addressing the Memory Bottleneck Problem of Deep Learning Hardware.”
“This recognition is a testament to his innovative research and dedication to pushing the boundaries of technology,” said ECE Chair Mark Nelms. “Dr. Sadi’s work not only advances the field of microelectronics, but also paves the way for more efficient, scalable and cost-effective solutions in semiconductor manufacturing. This achievement underscores the importance of fostering cutting-edge research that can drive technological progress and economic growth. We are incredibly proud of his accomplishments and look forward to the continued impact of his contributions.”
How will Sadi’s newest project work? By breaking larger, planar chips into multiple smaller and reusable ones and connect those onto packages.
“The smaller chiplets achieve higher yields due to reduced defects from the reduced area,” he said. “Moreover, chiplet technology allows heterogeneous integration where you can combine emerging technologies such as resistive RAM and magnetic RAM with regular semiconductors.”
Sadi will also use this research to create educational materials and open-source tools to help design advanced chiplet-based hardware, develop a skilled workforce in computer systems and AI/ML by encouraging participation from undergraduates, underrepresented groups and K-12 students.
Sadi said the ever-increasing demand for computing power will eventually lead to deeper vertical stacking in the industry.
“This research will address some of the fundamental challenges of enabling this and produce ideas to solve those,” he said. “Moreover, future computer-aided design tools will extensively incorporate AI in electronic design automation (EDA) to push for better performance, power, area and cost, and this innovative use of AI in EDA is one of the central themes of this project.”
Media Contact: , jem0040@auburn.edu, 3348443447
Mehdi Sadi is developing artificial intelligence/machine learning-assisted co-design methodologies to enhance the power, performance, reliability and cost-efficiency of next-generation AI hardware.
