ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2011, MWF 11AM, Broun 306
Course Syllabus,
Grades,
Statistics
Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE
Teaching Assistant: Jia Yao, 334-844-1864, B309,
consulting hours: WF 9:00-11:00AM.
EXAM SCHEDULE:
Test 1, Monday, 3/28/11, 11:00-11:50AM, Broun 306, use of books, notes, etc., permitted,
statistic.
Test 2, Friday, 4/15/11, 11:00-11:50AM, Broun 306, use of books, notes, etc., permitted,
statistic.
Final Exam, Tuesday, May 3, 2011, 12:00-2:30PM, Broun 306, use of books, notes, etc., permitted,
statistic.
PROJECT:
Spring 2011 Project Assignment, Friday, 1/28/11
Part 1 ISA, report due Friday, 2/11/11
Part 2 Datapath, report due Friday, 3/4/11
Part 3 Datapath Verification, report due Friday, 3/11/11
Part 4 Control Unit, report due Friday, 4/1/11
Part 5 Hardware Implementation and a working processor demo, report due Monday, 4/18/11
INSTRUCTIONS FOR DEMO:
1. Briefly describe what is implemented, what program you will run and what result is expected.
2. Run the program pointing to the functions of the buttons you press. Let the viewer examine the result.
3. Offer to make a change to some parameter to a viewer selected value and rerun the demo.
4. Total duration of demo: FIVE MINUTES.
Part 5 Reports:
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Project feedback from Fall 2010 students:
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Project feedback from Spring 2010 students:
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Project feedback from Fall 2009 students:
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Project feedback from Spring 2009 students:
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Project feedback from Fall 2008 students:
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Project feedback from Spring 2008 students:
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Project feedback from Fall 2007 students:
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VHDL references and relevant files for Project:
Guest Lecture by V. Nelson: Modeling and Simulating ASIC Designs with VHDL, 8/20/10
VHDL Review (Lecture from Fall 2009)
Modeling for Synthesis (Lecture from Fall 2009)
Overview of VHDL by Prof. Stroud
References on VHDL by Prof. Stroud
Lectures from Prof. Nelson's CAD course
Altera Quartus II and DE2 manual
Leonardo Spectrum for Altera HDL Synthesis Manual
Altera MegaWizard Plug-In Manager Manual
Run_time_content_editable_memory_tutorial.pdf
VHDL Files: hexto7seg.vhd,
regfile.vhd
HOMEWORK:
Homework 1, assigned 1/24/11, due 1/31/11.
Homework 2, assigned 2/7/11, due 2/14/11.
Homework 3, assigned 2/21/11, due 2/28/11.
Homework 4, assigned 3/7/11, due 3/21/11
Homework 5, assigned 4/8/11, due 4/18/11.
Homework 6, assigned 4/18/11, due 14/25/11.
LECTURES: See webpages of most recent years.
PREVIOUS OFFERINGS BY PROF. V. AGRAWAL:
Fall 2010,
Spring 2010,
Fall 2009,
Spring 2009,
Fall 2008,
Spring 2008,
Fall 2007,
Spring 2007,
Fall 2006,
Fall 2005,
Fall 2004