9. Short Channel Effect and Reverse Short Channel Effect

9.1. Objectives

• visualizing short channel effects
• understanding short channel effect
• understanding reverse short channel effect
• explore halo doping’s impact
• understand halo doping’s impact
• learn to formatting 2-D contours to make meaningful comparisons between structures

9.2. Required Programs

• sde
• sdevice
• tecplot_sv
• inspect

9.3. Reading Assignment

Read section 3.2, Short Channel MOSFET, on page 175. There is not much discussion on halo doping, other than a brief mentioning in passing in the later sections.

9.4. TCAD Simulations Required

You pretty much can take the existing .tdr files and existing command files to practice this yourself.

To see obvious short channel effects, try simulating Id-Vg and Id-Vd with the .tdr files saved for the 45nm and 1um MOSFETs. Try varying the halo doping level. A low halo doping of 1e16 is used as “no halo” in this chapter. The default halo doping is 1.5e18.

Below I will focus on the 45nm and 1um comparison, at Vg=0V, Vd=Vdd (1.2V), for both with and without halo doping.

9.5. 2-D Potential Contours and Ec

Let us consider non-halo devices first.

Launch tecplot_sv, load in the tdr files for non-halo 45nm and 1um devices, at Vg=0V and Vd=Vdd (1.2V).

Choose your settings so that you can see the actions going on in the channel region. Make x and y axis independent in axis settings so that we can maximize the screen space. Most of the action is at the surface, so we want to use our vertical space to show only the actions at the surface.

Similarly, use different x-axis range for short channel and long channel devices, at least do this for the contour plots.

Then take a 1D cut along the surface. Play with your settings for best visual effects.

The 2-D potential contours and surface conduction band energy plots for the 45nm and 1um devices are shown in figure 1. Biasing conditions are Vg=0V and Vd=Vdd, which represent the worst case from a standby power standpoint in VLSI circuits.

Figure 1: 2-D potential and 1-D surface conduction band energy along channel comparison between 45nm and 1um devices. Vg=0V, Vd=Vdd.

You could of course also plot out conduction band contour plots. I have indeed done so. Personally I find it more visually pleasant to look at potential contours and surface conduction band energy plots.

I have forced tecplot_sv to use the same contour levels in both channel lengths, to ease comparison. This is not default setting, so you want to keep this in mind in future comparisons.

A number of useful observations can be made:

1. Surface potential in the 1um device is well behaved, uniform along the channel. Potential contours are largely parallel to the surface.
2. Potential in the channel is much higher in the 45nm device.
3. Potential below the surface, also called sub-surface, is much higher in the 45nm device.
4. We cannot tell any laterally uniform region in the 45nm device.
5. The depletion boundary, indicated by the white line, is much deeper in the 45nm device for the same gate voltage. This is an indication of lower threshold voltage in the 45nm device.
6. At the surface, the potential barrier faced by source electrons is much lower in the 45nm device. As we have shown in previous classes, this barrier lowering at short channel length is strongly dependent on the drain voltage, and thus called drain induced barrier lowering (DIBL).
7. DIBL is non-existent in the long channel device.

Explore yourself to look at about everything you can think of, potential, conduction band energy Ec, eDensity n, eCurrentDensity jn, eVelocity vn.

Electron density is compared in figure 2. There are lot more electrons in the surface region of the channel in the 45nm device than in the 1um device.

Figure 2: 2-D contours and 1-D surface plot of eDensity n along channel in 45nm and 1um devices. Vg=0V, Vd=Vdd.

As you go along with your exploration, save some screen shots for later use. I have generated tons of such plots in preparation for this year’s lecture alone. You likely will need to redo your plots a few times before you are satisfied with its looks.

9.6. Id-Vg

figure 3 shows Id-Vg at Vd=0.05V and Vdd in 1um and 45nm devices with a low halo doping level that is much smaller than substrate doping level. We will refer to this as “without halo”, for all practical purposes.

Figure 3: Id-Vg at Vd=0.05V and Vdd in 1um and 45nm devices without halo, realized with a low halo doping level.

Note that in subthreshold region, Id is about the same for Vd=0.05V and Vdd in the 1um device, as expected from ideal long channel transistor subthreshold theory. In the 45nm device, the Id at Vd=0.05V in subthreshold region shows very weak gate control. The situation is even worse at Vd=Vdd.

With a high halo doping level, the gate control over in the 45nm device Id is much improved, as can be seen from figure 4. Id turns off with decreasing Vg much more effectively. The drain voltage still has much more impact on subthreshold current than in the 1um device, but gate control is still quite obvious.

Figure 4: Id-Vg at Vd=0.05V and Vdd in 1um and 45nm devices with a high halo doping level.

Let me point out in passing that in the 1um halo device, the subthreshold Id at Vd=Vdd is higher than at Vd=0.05V by a larger amount than in the 1um device without halo. This cannot be explained by long channel transistor theory, and is unique to halo doping. Intuitive explanations were proposed in recent years, interested students are encouraged to read relevant research papers.

9.7. Threshold Voltage vs Gate Length

Historically, short channel effect (SCE) is mainly used to refer to the decrease of threshold voltage with decreasing gate length. There are many other physical effects at short gate length of course. There were numerous publications on the topic at one time, I personally also published several papers on the topic back in the early 90s as a grad student.

figure 5 shows the linear region threshold voltage obtained from peak gm extrapolation as a function of gate length, for devices with and without halo doping (implemented using different doping levels).

Figure 5: Vd=0.05V threshold voltage from peak gm extrapolation versus gate length. Both halo and non-halo devices are shown.

Without halo doping, threshold voltage decreases with gate length, as the source/drain junction lateral field penetrates into the channel, raising the surface potential. As a result, less gate voltage is required for the surface potential to reach the same threshold value. Since 45nm is so short compared to the lateral depletion width of the source/drain to channel junctions, the whole channel is now under the influence of the source/drain junctions.

With a high drain voltage of Vdd, the situation is only worsened. If you repeat the surface plot for multiple Vd, you will find that the peak Ec point will move towards the source with increasing Vd, and the barrier will be lowered with increasing Vd too. I have shown you one such plot in class, you can generate one yourself.

This of course is a way too simplified picture of reality, which is inherently 2-D, while threshold surface potential was a concept from 1-D MOS structure analysis. When we have so much lateral surface potential variation, most of the concepts such as threshold surface potential, even threshold voltage, lose its classic meanings. However, in practice, we continue to use the long channel like equations, so we continue to use these concepts like threshold voltage. We should keep in mind that more complex nature of short channel device.

We have seen from figure 5 that with a high halo doping level of 1.5e18, the threshold voltage decrease with gate length scaling has been greatly reduced. In other words, halo doping is effective in suppressing short channel effect. Next let us take a deeper look at how halo helps suppressing short channel effect.

9.8. How Halo Helps

Recall from Elec6700 that PN junction depletion thickness can be reduced by increasing doping. The situation is similar. The pocket halo doping placed near the source/drain reduces the depletion thickness of the source/drain to channel junctions. Effectively, the lateral distance over which the source/drain have control is reduced, or its impact is weaker for the same distance from source/drain.

To illustrate this, 2-D potential contours of 45nm and 1um devices with and without halo doping are compared in figure 6. Biasing conditions are the same as above, Vg=0V and Vd=Vdd.

Figure 6: 2-D potential contour at Vg=0V and Vd=Vdd, for 45nm and 1um MOSFETs, with and without halo doping.

It takes some patience and efforts to have all the plots formatted in the right way with the right scale for x and y axes, suitable for apple-to-apple comparison. The following considerations went into formatting these plots:

1. The same scale is used for the x and y axes for the same gate length.
2. The y-axis scale for all four plots is made the same to allow comparison of depletion thickness.
3. The x-axis scale for the 1um contours is set to a larger value than for the 45nm contours to make the whole channel visible. Default is the same x-axis scale for short and long channel, which means you can only see the center portion of the longer device.

Without halo, in the 45nm device, the whole area between source and drain is flooded with high potential, and the depletion region is much thicker as indicated by the white curve, the depletion boundary. Source/drain’s control over the channel is effectively reduced by the halo doping.

In the 1um device, depletion thickness is clearly reduced in the halo doping region. The depletion boundary moves upward right where the halo doping is.

Note

The increase of Vth with decreasing gate length is due to an increase of the average channel doping, as well as the reduced short channel effect. Again, this is an approximate picture, as the doping is not uniform along the whole channel laterally.

9.9. Reverse Short Channel Effect (RSCE)

An inspection of figure 5 immediately shows the signature of halo doping, that is, an increase of threshold voltage with decreasing channel length, known as reverse short channel effect (RSCE), as it is opposite to short channel effect, i.e. decrease of threshold voltage with decreasing gate length. For shortest gate length, Vth starts to decrease again.

9.10. VTI and DIBL effects

figure 7 shows current defined threshold voltages and DIBL versus gate length. Both halo and non-halo devices are shown. For short lengths, DIBL is stronger without halo.

However, with halo, DIBL is strong with halo in the long channel devices. This is not an error. It is real. The exact physics on this is beyond the scope of this class. I can recommend some recent research papers on this topic if interested.

DIBL is fortunately weak in long channel devices to begin with, so some degradation due to halo does not present a big problem. It is mainly a concern for analog circuits that often use long channel devices. The consequence is an increase of the output conductance.

Figure 7: Current defined threshold voltages and DIBL versus gate length. Both halo and non-halo devices are shown.

9.11. Subthreshold Swing

The benefits of halo also show up as much reduced subthreshold swing at shorter gate length, as can be seen from figure 8. The improvement for Vd=Vdd is even more obvious.

Figure 8: Subthreshold swing (SS) versus gate length for linear and saturation operation. Both halo and non-halo devices are shown.

The physics is similar to how halo reduced short channel effect.

9.12. Homework

As we have just had a midterm project, we do not have any official new homework this week. Think a bit more about what you did, the doubts you have, and how you can better organize your data and plots to support your conclusions. Use the suggestions I made during today (Nov 4)’s lecture.

I also encourage you to reproduce figure 5 yourself. I will address issues you may experience next class.

Read section 3.2, Short Channel MOSFET, on page 175.