ELEC 4200 Digital System Design

ELEC 4200 Digital System Design
Fall 2022
Lecture: WF, 12:00 p.m. - 12:50 p.m., Broun 125
Lab Section 1: Thursday, 12:30 p.m. - 3:20 p.m., Broun 320
Lab Section 2: Thursday, 8:00 a.m. - 10:50 a.m., Broun 320

Back to Teaching

Link to Course Syllabus

Link to Lab Handout

Instructor:
Ujjwal Guin, Assistant Professor

GTA:

Yuxi Zhao, Broun 354, Office Hours - Tuesday, 2:00-3:00 p.m.

Text Book:

Digital Logic Circuit Analysis and Design, 2nd Ed., (eText), V. P. Nelson, B. D. Carroll, H. T. Nagle, J. D. Irwin, Pearson Education, Inc. 2021.

Reference Book:

Digital Design: With an Introduction to the Verilog HDL 5th Edition by M. Morris R. Mano and Michael D.Ciletti, ISBN-13: 978-0132774208.

Design and Simulation Software: If you want to simulate & synthesize on your own PC, outside of lab.

Test Schedule:

Test 1, TBD, 12:00 p.m. - 12:50 p.m., Broun 125, use only 4 sheets of paper.
Test 2, TBD, 12:00 p.m. - 12:50 p.m., Broun 125, use only 4 sheets of paper.
Final Exam, Tuesday, December 6, 12 noon - 2:30 p.m, Broun 125, use only 4 sheets of paper.

Lecture Notes:

Introduction to ASIC design:

ASIC Design Flow

Logic Design Review:

Combinational Circuit Design Process (Text Chaps. 2 and 3)
Sequential Circuit Design Process (Text Chaps. 4 and 5)
Flip-flops and Latches (Text Chap. 4)
VHDL (Text Appendix B, Examples in Chaps. 2-5 and 7)

Lecture slides:

VHDL Tutorials:

Verilog (Text Appendix A):

Programmable Logic Devices and FPGAs:

Overview of FPGAs (slides; Text: Chap. 7.2)
Programmable Logic Devices (slides; Text: Chap. 7.3)
PALs and PLDs (document)

Xilinx Artix-7 FPGA Web Page (data sheets, user guides, examples, etc.):

Artix-7 Data Sheet
7 Series FPGAs Configurable Logic Block User Guide
Other user guides on Artix-7 web page

Digilent Nexys A7 Artix-7 FPGA Board Web Page and Resources:

FPGA Configuration:

Xilinx 7 Series FPGAs Configuration User Guide

Boundary Scan in FPGAs:

Testing and Boundary Scan Overview Slides
Configuration of Spartan-II using Boundary Scan
Spartan 3 Configuration User Guide (see JTAG section)
Boundary Scan Operation via ISE-IMPACT (by Gefu Xu)

PicoBlaze:

PicoBlaze KCPSM6 User Manual (Ken Chapman)
PicoBlaze 8-bit Embedded Microcontroller User Guide
PicoBlaze KCPSM6 Assembler and Tutorial files (Lab files: .zip file)
Xilinx PicoBlaze 8-Bit Embedded Microcontroller Web Page
Design Files Download Page

Lab Exercises and Homework:

Lab Handout :

Special homework (digital logic design review)
Lab #0 Tutorial - (08/19) Introduction to lab hardware & software
Nexys A7 - 100T Master Constraints File
Lab 1: Modeling Concepts
Lab 2: Numbering Systems
Lab 3: Multi-Output Circuits: Encoders, Decoders, and Memories
Lab 4: Tasks, Functions, and Testbench
Lab 5: Modeling Latches and Flip-flops
Lab 6: Modeling Registers and Counters
Lab 7: Behavioral Modeling and Timing Constraints
Lab 8: Architectural Wizard and IP Catalog
Lab 9: Counters, Timers and Real-Time Clock
Lab 10: Sequential System Design Using ASM Charts
Lab 11: "Design your own lab project"
You are to:

Identify a problem: Come up with an idea for a system design to be implemented on the Nexys A7 board that will perform some "application".
Formulate the problem:Write a set of requirements for the proposed system.
Solve the problem: Design, implement, verify, and test the design in lab.
Report: The lab report for this project should have at least three sections, corresponding to the headings listed above (identify, formulate, and solve the problem).

Reference Material for Lab Exercises:

Vivado Quick Start Guide
Digilent Nexys A7 Web Page and Resources
- Nexys A7 Reference Manual
- Nexys A7 Schematic
Xilinx Artix-7 FPGA Web Page (data sheets, user guides, examples, etc.)

To simulate & synthesize on your own PC before the lab:
- Link to free Vivado Design Suite WebPack
- Link to free Aldec Active-HDL Student Edition