ELEC 4200 Digital System Design
Fall 2019, WF, 1:00 p.m. - 1:50 p.m., Broun 235 (Lecture)
M, 4:00-6:50 p.m., Broun 320 (Lab: Section 1)
W, 5:00-7:30 p.m., Broun 320 (Lab: Section 2)
Back to Teaching
Link to Course Syllabus
Link to Lab Handout
Instructor: Ujjwal Guin, Assistant Professor
Text Book:
- Digital Logic Circuit Analysis and Design, 2nd Edition (Preliminary Draft), V.P. Nelson, B.D. Carroll, H.T. Nagle, J.D. Irwin, to be published by Pearson Education, Inc. in 2020.
Design and Simulation Software: If you want to simulate & synthesize on your own PC, outside of lab.
Test Schedule:
- Test 1, Oct 4, 1:00 p.m. - 1:50 p.m., Broun 235, use only 4 sheets of paper.
- Test 2 (Optional), Nov 15, 1:00 p.m. - 1:50 p.m., Broun 235, use only 4 sheets of paper.
- Test 3, Dec 4, 1:00 p.m. - 1:50 p.m., Broun 235, use only 4 sheets of paper.
Lecture Notes:
Lab Exercises and Homework:
- Lab Handout :
- Special
homework (digital logic design review)
-
Lab #0 Tutorial - (9/19-21) Introduction
to lab hardware & software
Nexys4 Master Constraints File
-
Lab #1 - (8/26-28) Combinational Logic
Design Using Logic Equations
VHDL model template file for Lab 1
-
Lab #2 - (9/9-11) Sequential Logic
Design Using Logic Equations
VHDL model template file for Lab 2
-
Lab #3 - (9/16-18) Combinational Logic Design
Using a Behavioral Model
Viewing
and editing implemented designs in Vivado
-
Lab #4 - (9/23-25) Sequential Logic
Design Using a Behavioral Model
Post-Implementation
Timing Simulation
-
Lab #5 - (9/30-10/2) Parameterized VHDL
Universal Register/Counter
VHDL debounce.vhd
circuit model
-
Lab #6 - (10/7-9) Parameterized VHDL
Register File Design with Test Bench
- Lab #7 - (10/14-16) Hierarchical VHDL Modeling of Manually Controlled Display
System
- Lab #8 – (10/21-23) “Design your own lab project” You are to
- Identify a problem: Come up with an idea for a system design to be
implemented on the Nexys4 DDR board that will perform some “application”.
- Formulate the problem: Write a set of requirements for the proposed system.
Email your proposed project identification and formulation to Prof. Nelson during the week before Spring break, so that feedback can be provided on the appropriateness of the project as a one-lab session project.
- Solve the problem: Design, implement, verify, and test the design in lab.
- Report: The lab report for this project should have at least three sections, corresponding to the headings listed above (identify, formulate, and solve the problem).
- Lab #9 - (10/28-30) PicoBlaze Programming, Simulation and Synthesis.
Links to PicoBlaze User Manual, User Guide, Assembler and Tutorial files provided above.
- Lab #10 - (11/4-6) Interfacing external devices to PicoBlaze via input/output ports.
- Lab #11 - (11/11-13) Interfacing external devices to PicoBlaze via interrupt-driven operation.
- Lab #12 - (11/18-20, 12/2-4) PicoBlaze-Controlled Display System – Hint: One solution to bleeding and/or dim display problem is to add a 15-bit register at the output (for the 7 segments and 8 enable values) which is enabled by the write strobe (this will hold the 7-segment value plus the corresponding digit enable for the maximum amount of time until the next value is ready for display for good brightness with minimum bleeding).
- Reference Material for Lab Exercises:
- To simulate & synthesize on your own PC before the lab: