The VLSI Design & Test Seminar Series

seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Professor Emeritus: Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Spring 2014 schedule:

When: Wednesdays from 4-5:30pm

Where: Broun Hall room 235

Coordinator: Vishwani Agrawal

Invitation: If you are interested in presenting a seminar or defending your thesis/dissertation, please contact the coordinator.

Notes: The following is a tentative schedule (speakers/topics in blue text are not confirmed at this point). A link under Speaker is to an abstract of the presentation and a link under Topic is to a PDF file of the presentation slides.

Date	Speaker	Topic (w/ link to presentation slides after seminar date)
Jan 11	No Seminar	First Week of Classes
Jan 15	Vic Nelson	Functional IC test with the ADVANTEST T2000 GS system
Jan 22	Adit Singh	Better Than Worst Case Timing Design With Latch Buffers On Short Paths
Jan 29	Postponed to Feb. 12	University closed (snow)
Feb 5	Eric Ingram	Fault Injection for FPGA Testing on the ADVANTEST T2000
Feb 12	Michael Pukish	Comparison of Various Learning Machines in Computational Intelligence for Data Processing and System Modelling
Feb 19	Karthik N. Jayaraman	DVF4: A Dual Vth Feedback Type 4-Transistor Level Converter
Feb 26	Vijay Sheshadri	Power-Aware System-on-Chip Test Optimization through Frequency and Voltage Scaling (PhD defense)
Mar 5	Vishwani Agrawal	Specification Test Minimization for Given Defect Level
Mar 12	No seminar	Spring break
Mar 19	Praveen Venkataramani	Functional Testing Using Advantest T2000GS
Mar 26	Chao Han	Improving CMOS Open Defect Coverage Using Hazard Initialized Tests
Apr 2	Sidhu Gunesekar	Finding Optimum Clock Frequencies for Aperiodic Test (MS defense)
Apr 9	Jie Zou	Combining LOC and LOS Tests for TDF Coverage Improvement (MEE defense)
Apr 16	Victor P. Nelson	Automatic Test Pattern Generation (ATPG) with Tessent “FastScan” (Cancelled – University closed)
Apr 23	Abhjit Chatterjee	SELF-AWARE REAL-TIME WIRELESS COMMUNICATION AND SIGNAL PROCESSING SYSTEMS: ADAPTATION FOR PERFORMANCE, LOW POWER AND ERROR RESILIENCE

Links to previous semesters of the VLSI Design & Test Seminar Series:

Spring 2012: Coordinator Chuck Stroud

Fall 2011: Coordinator Vishwani Agrawal

Spring 2011: Coordinator Adit Singh

Fall 2010: Coordinator Adit Singh

Spring 2010: Coordinator Chuck Stroud

Fall 2009: Coordinator Vishwani Agrawal

Spring 2009: Coordinator Adit Singh

Fall 2008: Coordinator Chuck Stroud

Spring 2008: Coordinator Vishwani Agrawal

Fall 2007: Coordinator Adit Singh

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud