ELEC 5250/6250/6256 - Computer-Aided Design of Digital Circuits

Fall Semester, 2018

Instructor: Victor P. Nelson, Professor of ECE

Syllabus: ELEC 5250/6250/6256

Important Dates:

· Labor Day Holiday: Monday, September 3

· Midterm Exam (date TBA)

· Fall Break: Thursday-Friday, October 11-12

· Thanksgiving Holidays: Monday-Friday, November 19-23

· Last Class Day: Friday, December 7

· Final Exam: Wednesday, December 12, 8:00-10:30 a.m.

Homework Assignments:

1. Wednesday, August 22: Three-to-four page report describing a commercial ASIC (function, technology, characteristics, CAD tools used, etc.) This must be some commercial ASIC that has been designed for a particular application within the past two years. Do not report on a “platform” FPGA/ASIC, microcontroller, or IP block – report on an ASIC produced for a particular application.
2. Friday, August 24: (Prerequisite review) Modulo-6 counter design
3. Thursday, September 6: Modulo-6 counter Verilog models
4. Monday, September 10: PART 1: Modulo-6 counter simulations (do file)
5. Thursday, September 13: PART 2: Modulo-6 counter simulations (testbench)
6. Wednesday, September 19: Binary divider Verilog model (draft models/no grade)
7. Monday, September 24: Binary divider Verilog model and simulation

Wednesday, October 3: Midterm Quiz

8. Friday, October 5: Synthesis of Verilog model(s)
9. Tuesday, October 15 (11:00 am): Timing simulation and analysis
10. Monday, October 29 (in class): Block layout from Innovus
11. Monday, November 5: Faults and ATPG
12. Monday, November 12: Design for Testability
13. Friday, December 7: Final Exam Project (ELEC 5250) (ELEC6250)

Course Topics & Lecture Slides (linked PDF files):

1. SoCs and ASICs
2. ASIC Technologies and Design
3. ASIC Cost
4. ASIC Design Process
5. Verilog modeling for ASIC design
6. Simulation of Verilog models
7. Verilog testbenches
8. Modular Verilog models
9. Synthesis with Synopsys Design Compiler
10. Post-synthesis simulation with delay data
11. CMOS IC fabrication processes
12. Physical design of blocks of standard cells
13. Faults and test-pattern generation
14. Automatic test-pattern generation and fault simulation
15. Advantest T2000 tester
16. Design for testability (DFT)
17. Built-in Self Test
18. JTAG/Boundary Scan
19. Top-Level Chip Pads and Layout
20. Virtuoso, AMI06-UofU Technology, and Top-Level Layout
21. Post-Layout Verification with Calibre
22. Post-Layout Simulation with ADiT
23. Design with Intellectual Property Cores

Reference Material:

• Application-Specific Integrated Circuits, Michael J. S. Smith, Addison Wesley Longman, Inc., 1997. Electronic version: http://www10.edacafe.com/book/ASIC/ASICs.php
• Other resources at EDACafe: http://www.edacafe.com/
• Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Erik Brunvand, Addison Wesley, 2010 (soft cover)
• Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Hubert Kaeslin, Cambridge University Press, 2008.
• CMOS Circuit Design, Layout, and Simulation, 2^nd Ed., R. Jacob Baker, Wiley-Interscience, 2008
• CMOS VLSI Design, 3^rd Ed., Neil H.E. Weste and David Harris, Addison Wesley, 2005.
• International Technology Roadmap for Semiconductors: http://www.itrs2.net/

Useful CAD Tool Links:

• Modelsim PE Student Edition Download: http://www.model.com/resources/student_edition/download.asp
• Access to Cadence, Synopsys and Mentor Graphics tools on a college Linux server requires a tool such MobaXterm, which integrates a secure shell and X server into one package. Alternatively you can use a separate secure shell (such as SecureCRT) and an X server (such as Xming).
• Connect and log into server: gate.eng.auburn.edu.
• Sample .bashrc file to set up paths/variables on Linux server for Synopsys, Cadence and Mentor Graphics tools.
• Copy to home directory on linux system and name the file .bashrc

· Mentor Graphics ADK standard cell HDL model files:

adk.vhd (VHDL cell models)

adk_comp.vhd (VHDL component declaration package)

adk.v (Verilog cell models)

On linux server at

/linux_apps/ADK3.1/technology

• Mentor Graphics GDK standard cell HDL model files:

gdk.vhd (VHDL cell models)

gdk_comp.vhd (VHDL component declaration pkg),

gdk.v (Verilog cell models)

On linux server at

/linux_apps/mentor/pyxis/Pyxis_SPT_HEP/ic_reflibs/external_libs/GDKgates/GDKgates_utilities/hdl_libs

• Linux commands to open Mentor Graphics documentation (assuming you used the above .bashrc file):
• mgcdocs $LEO_DOCS (LeonardoSpectrum documentation)
• mgcdocs $AMS_DOCS (Questa ADMS documentation, including Questa SIM - formerly ModelSim)
• Auburn ECE "Computing Tools" Resources
• Designing Standard Cells ASICs with the ASIC Design Kit (ADK) and Mentor Graphics Tools
• Mentor Graphics Tools Seminar

· AU Student-Authored Tutorials on Mentor Graphics Tools, ASIC Design Kit (ADK) Standard Cells, Scan-Based Design-for-Test

· Haihua Yan/Gefu Xu

· Ayoush Dixit/Harshit Poladia

• Santa Clara University – VLSI CAD Tutorials for Mentor Graphics
• Virginia Commonwealth University Mentor Graphics EDA Tool Tutorials
• North Carolina State (T. R. Harris) Design Architect Tutorials (buses and hierarchy)
• Documentation on TSMC 0.35um Pads (Tanner Consulting and Engineering Services)
• chiptalk.org – IC Design and EDA Tools Resources
• Virginia Tech “VLSI Design World” (Cell Libraries, CAD Tool Tutorials)
• North Carolina State University – EDA Wiki (NCSU Cadence Design Kit – CDK & Tutorials)
• Best of the Web – Electronic Design Automation Links

VHDL Links

• VHDL Overview (ELEC 5200/6200)
• Professor Stroud's ELEC 4200 VHDL Resources

· “Nandland” FPGA/VHDL/Verilog Tutorials

• EDA Industry Working Groups for VHDL, Verilog, and related standards
• Hamburg VHDL Archive (Good source of VHDL documentation, models & tools)
• A comparison of VHDL andVerilog with examples of equivalent models in each language
• A comprehensive set of overviews of VHDL, Verilog, System C, PERL, and TCL/TK
• VHDL Cookbook - a 111 page PDF pre-publihed version of The Designer's Guide to VHDL
• A VHDL tutorial (by Weijun Zhang, U.C. Riverside) with good examples and links to reference and related material