Fall 2013
Instructor: Victor P. Nelson (nelsovp@auburn.edu, Office: Broun 326)
A RISC CPU is to be designed in the VHDL modeling language, verified via the Mentor Graphics "ModelSim" or Aldec Active-HDL simulator, and implemented on the Altera DE2 FPGA board using Alteras Quartus II software. The project consists of six parts as defined below. Due dates will be listed above as the semester progresses. It is highly advised that you read problem definitions of all six parts before actually starting with Part 1, i.e., Instruction Set Architecture (ISA). Please submit only the List Format (do not submit wave format) of the simulation results in part 3, part 4, and part 5. Always annotate your simulation results. Maintain a single folder for submitting the project parts. When submitting a later part, all the previous parts need to be in the folder.
1.
Wednesday,
8/21/13: Introduction to Computer Architecture
2.
Friday, 8/23/13: History of Computers
3.
Monday, 8/26/13: Introduction to VHDL
4.
Wednesday, 8/28/13: Introduction to VHDL (continued)
5.
Friday, 8/30/13: Introduction to VHDL (continued)
6.
Monday, 9/2/13: Labor Day Holiday
7.
Wednesday, 9/4/13: Introduction to VHDL
(continued),
Simulation in Modelsim/Active-HDL
8.
Friday, 9/6/13: Simulation in Modelsim/Active-HDL
9. Monday, 9/9/13: Instruction Set Architecture - MIPS (Text Chapter 2)
10. Wednesday, 9/11/13: Instruction Set Architecture - MIPS (Text Chapter 2)
11. Friday, 9/13/13: Instruction Set Architecture - MIPS (Text Chapter 2)
12. Monday, 9/16/13: Instruction Set Architecture - MIPS (Text Chapter 2)
13. Wednesday, 9/18/13: Instruction Set Architecture - Other (Text Chapter 2)
14.
Friday, 9/20/13: CPU Datapath
Design (Text Chapter 4)
15.
Monday, 9/23/13: CPU Datapath
Design (Text Chapter 4)
16.
Wednesday, 9/25/13: CPU Datapath
Design (Text Chapter 4)
17.
Friday, 9/27/13: System Performance (Prof. Singh)
(Text - Chapter 1)
18.
Monday, 9/30/13: CPU Datapath
Design (Text Chapter 4)
19. Wednesday, 10/2/13: CPU Datapath Control Unit (Text Chapter 4),
Take-home
Midterm Quiz #1 distributed at end of class.
20. Friday, 10/4/13: Midterm Quiz #1 due at start of class.
Pipelined Datapath Design (Text Chapter 4)
21. Monday, 10/7/13: No class meeting
22. Wednesday, 10/9/13: CPU Datapath Pipelined Design (Text Chapter 4)
23. Friday, 10/11/13: CPU Datapath Pipelined Design (Text Chapter 4)
24. Monday, 10/14/13: CPU Datapath Pipelined Design (Text Chapter 4)
25. Wednesday, 10/16/13: CPU Datapath Pipelined Design (Text Chapter 4)
26. Friday, 10/18/13: CPU Datapath Pipelined Design (Text Chapter 4)
27. Monday, 10/21/13: CPU Datapath Pipeline Examples (Scans)
28. Wednesday, 10/23/13: Memory Systems, Cache Memory (Text Chapter 5)
29. Friday, 10/25/13: Cache Memory (Text Chapter 5)
30. Monday, 10/28/13: Cache Memory (Text Chapter 5)
31. Wednesday, 10/30/13: Cache Memory (Text Chapter 5)
32. Friday, 11/1/13: Cache Memory , Virtual Memory (Text Chapter 5)
33. Monday, 11/4/13: Virtual Memory (Text Chapter 5)
34. Wednesday, 11/6/13: Virtual Memory (Text Chap. 5), ALU design (Text Chap. 3)
35. Friday, 11/8/13: Midterm Quiz #2 (in class)
36. Monday, 11/11/13: ALU design (Text Chapter 3)
37.
Wednesday: 11/13/13: ALU design (Text Chapter
3)
38.
Friday, 11/15/13: ALU design (Text Chapter
3)
39.
Monday, 11/18/13 Floating-Point ALU Design
(Text Chapter 3)
40.
Wednesday, 11/20/13 Floating-Point ALU Design
(Text Chapter 3)
41.
Friday, 11/22/13 Disk and Flash Storage (Text Chapter 6)
42.
Monday, 12/2/13: Memory and I/O (Text Chapter 6)
43.
Wednesday, 12/4/13: Memory
and I/O (Text Chapter 6)
44.
Friday, 12/6/13: Advanced topics
FINAL EXAM: Friday,
December 13, 12:00-2:00 pm
o Run-Time Content Editable
Memory using MegaWizard Plug-In Manager
o Sample RAM_init.mif (memory initialization file)