Lecture (Broun 306):
8:00-8:50
a.m. Tuesday & Thursday
Lab (Broun 320):
·
Section 1: 4:00-6:50 p.m. Monday
· Section 2: 5:00-7:50 p.m.
Wednesday
Text: Digital Logic Circuit
Analysis and Design, 2nd Edition (Preliminary Draft), V.P. Nelson, B.D. Carroll,
H.T. Nagle, J.D. Irwin, to be published by Pearson Education, Inc. in 2020.
Design and Simulation Software
If you want to
simulate & synthesize on your own PC, outside of lab.
Link
to free Vivado Design Suite WebPack
Link
to free Aldec Active-HDL Student Edition
Lecture Notes:
Introduction to ASIC design:
Logic Design Review:
Combinational Circuit Design Process (Text Chaps. 2 and 3)
Sequential Circuit Design Process (Text Chaps. 4 and 5)
Flip-flops and Latches (Text Chap. 4)
VHDL (Text Appendix B, Examples in Chaps. 2-5 and
7)
Lecture
slides:
VHDL
tutorials:
VHDL Entities, Architectures, and Processes
VHDL Names, Signals, and Attributes
VHDL Parameterized RAM Modeling
VHDL Sequential Logic Modeling
“Nandland” FPGA/VHDL/Verilog Tutorials
Verilog (Text Appendix A)
Programmable Logic Devices and FPGAs:
Overview of FPGAs (slides; Text:
Chap. 7.2)
Programmable Logic Devices (slides; Text:
Chap. 7.3)
PALs and PLDs (document)
Xilinx
Artix-7 FPGA Web Page (data sheets,
user guides, examples, etc.)
7
Series FPGAs Configurable Logic Block User Guide
Other user guides on Artix-7 web page
Digilent
Nexys4 DDR Artix-7 FPGA Board Web Page and Resources
FPGA Configuration:
Xilinx 7
Series FPGAs Configuration User Guide
Boundary Scan in FPGAs:
Testing and Boundary
Scan Overview Slides
Configuration
of Spartan-II using Boundary Scan
Spartan 3
Configuration User Guide (see JTAG section)
Boundary
Scan Operation via ISE-IMPACT (by Gefu Xu)
PicoBlaze:
PicoBlaze
KCPSM6 User Manual (Ken Chapman)
PicoBlaze 8-bit Embedded Microcontroller User Guide
PicoBlaze KCPSM6 Assembler and Tutorial files (Lab
files: .zip file)
Xilinx PicoBlaze 8-Bit Embedded Microcontroller Web Page
Lab Exercises and
Homework:
Special
homework (digital logic design review) Due
Tuesday, Jan. 15
Lab #0 Tutorial - (1/14-16) Introduction
to lab hardware & software
Nexys4 Master Constraints File
Lab #1 - (1/22-23) Combinational Logic
Design Using Logic Equations
-
VHDL model template file for Lab 1
Lab #2 - (1/28-30) Sequential Logic
Design Using Logic Equations
-
VHDL model template file for Lab 2
Lab #3 - (2/4-6) Combinational Logic Design
Using a Behavioral Model
-
Viewing
and editing implemented designs in Vivado
Lab #4 - (2/11-13) Sequential Logic
Design Using a Behavioral Model
-
Post-Implementation
Timing Simulation
Lab #5 - (2/18-20) Parameterized VHDL
Universal Register/Counter
·
VHDL debounce.vhd
circuit model
Lab #6 - (2/25-27) Parameterized VHDL
Register File Design with Test Bench
Lab #7 -
(3/4-6) Hierarchical VHDL Modeling of Manually Controlled Display
System
Lab
#8 – (3/18-20) “Design your own lab project” You are to
1. Identify a problem: Come up with an idea for a system design to be
implemented on the Nexys4 DDR board that will perform some “application”.
2. Formulate the problem: Write a set of requirements for the proposed system.
Email your proposed project identification
and formulation to Prof. Nelson during the week before Spring break, so that
feedback can be provided on the appropriateness of the
project as a one-lab session project.
3. Solve the problem: Design, implement, verify, and test the design in lab.
4. Report: The
lab report for this project should have at least three sections, corresponding
to the headings listed above (identify, formulate, and solve the problem).
Lab #9 - (3/25-27) PicoBlaze
Programming, Simulation and Synthesis.
·
Links to PicoBlaze User Manual, User Guide, Assembler and Tutorial
files provided above.
Lab #10 - (4/1-3) Interfacing external devices to PicoBlaze via input/output ports.
Lab #11 -
(4/8-10) Interfacing external devices to PicoBlaze
via interrupt-driven operation.
Lab #12 - (4/15-17, 22-24) PicoBlaze-Controlled Display System – Hint: One solution to
bleeding and/or dim display problem is to add a 15-bit register at the output
(for the 7 segments and 8 enable values) which is enabled by the write strobe
(this will hold the 7-segment value plus the corresponding digit enable for the
maximum amount of time until the next value is ready for display for good
brightness with minimum bleeding).
Reference
Material for Lab Exercises:
Digilent
Nexys4 DDR Web Page and Resources
Xilinx
Artix-7 FPGA Web Page (data sheets,
user guides, examples, etc.)
To simulate & synthesize on your own PC before the
lab session :
Link
to free Vivado Design Suite WebPack
Link
to free Aldec Active-HDL Student Edition