Flowchart: Process: Circuit Description in HDL

Flowchart: Process: Synthesis using Leonardo Flowchart: Process: Insertion of Scan-based Test Structure using DFTAdvisor Flowchart: Process: Schematic creation using Design Architect and Edif2Eddm Flowchart: Process: Design of Top-Level Schematic using Design Architect Flowchart: Process: Simulation of Top-Level using QsPro Flowchart: Process: Insertion of Delay Element using Design Architect Flowchart: Process: Determination of Test vectors using FastScan Flowchart: Process: Analog Transient Simulation using Accusim Flowchart: Process: Layout of the circuit using ICStation Flowchart: Process: Back Annotation of the extraction using Accusim Flowchart: Process: Insertion of PadFrame Flowchart: Process: Generation of GDSII Flowchart: Process: TestBench in HDL

                            DESIGN FLOW for MODIFICATION of ITC BENCHMARK CIRCUIT

                                       to ENABLE SCAN BASED DELAY FAULT DETECTION

                                                                                    created by Harshit Poladia & Ayoush Dixit