Bibliography






    1966-1969

  1. V. K. Jain and V. D. Agrawal, Directional Loudspeaker System for a Big Hall, J.I.T.E. (India), Vol. 12, pp. 29--35, 1966.
  2. S. K. Chatterjee and V. D. Agrawal and R. Chatterjee, Reactance Modulated Dielectric Rod Waveguide, J.I.E. (India), Vol. 43 Part ET2, pp. 103--114, 1968.
  3. Y. T. Lo and V. D. Agrawal, Removal of Blindness in Phased Arrays, URSI Conf., Boston MA, 1968, (Also Proc. IEEE Vol. 56 pp. 1586-1588 September 1968.) .
  4. V. D. Agrawal and Y. T. Lo, Distribution of Sidelobe Level in Random Arrays, Proc. IEEE, Vol. 57, pp. 1764--1765, 1969.

    5. 1970-1979

  5. Y. T. Lo and V. D. Agrawal and A. R. Panicali, A Review of the Theory of Random Arrays with Some Recent Results, Proc. 4th Colloquium on Microwave Communication, Budapest Hungary, 1970.
  6. V. D. Agrawal and D. R. Barkhurst, Vertically Polarized Dipole Evaluation - Final Report, EG&G Report AL-685 March 1 1972 EG&G Inc. Albuquerque N.M..
  7. V. D. Agrawal and Y. T. Lo, Mutual Coupling in Phased Arrays of Randomly Spaced Antennas, (Also IEEE Trans. Ant. Prop. Vol. AP-20 pp. 288-295 May 1972.) , Antenna Lab. Report No. 71-1 University of Illinois Urbana Illinois.
  8. V. D. Agrawal and Y. T. Lo, Anomalies of Dielectric Coated Gratings, Applied Optics, Vol. 11, pp. 1946--1951, 1972.
  9. V. D. Agrawal and P. Agrawal, An Automatic Test Generation System for Illiac IV Logic Boards, IEEE Trans. Comput., Vol. C-21, pp. 1015--1017, 1972.
  10. V. D. Agrawal, A Novel Technique of Electronic Scanning, Symposium on Sonar Systems and Ultrasonics, Indian Institute of Technology, New Delhi, May 3-5 1973.
  11. V. D. Agrawal and R. K. Arora, Scanning Transients in Phased Array Antennas, Proc. IEEE, Vol. 62, pp. 850--851, 1974.
  12. R. K. Arora and V. D. Agrawal, Frequency-Spread Associated with Fast Electronic Scanning, Proc. IEEE, Vol. 62, pp. 1175--1176, 1974.
  13. V. D. Agrawal, Comments on Beamwidth of Phased Arrays, IEEE Trans. Ant. Prop., Vol. AP-22, pp. 841--842, 1974.
  14. D. T. Shahani and V. D. Agrawal, An Experimental Phased Array Antenna, SRS-75-1, School of Radar Studies Indian Institute of Technology, New Delhi, 1975, Report No..
  15. P. Agrawal and V. D. Agrawal, On Improving the Efficiency of Monte Carlo Test Generation, Digest of Fifth Int. Fault Tolerant Computing Symposium, pp. 205--209, Paris France, June 18-20 1975.
  16. P. Agrawal and V. D. Agrawal, Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Networks, IEEE Trans. Comput., Vol. C-24, pp. 691--695, 1975.
  17. P. Agrawal and V. D. Agrawal, On Monte Carlo Testing of Logic Tree Networks, IEEE Trans. Comput., Vol. C-25, pp. 664--667, 1976.
  18. V. D. Agrawal and W. A. Imbriale, Dichroic Subreflector, 76-7323.A4-72, TRW Defense and Space Systems Group, Redondo Beach CA, 1976, Report No..
  19. V. D. Agrawal and W. A. Imbriale, Experimental and Theoretical Design of Dichroic Surface for a Spacecraft Antenna, IEEE Int. AP-S Symp., Amherst MA, 1976, (Digest pp. 105-108.) .
  20. V. D. Agrawal and W. A. Imbriale, Analysis of Frequency Selective Surfaces Printed on Dielectric Sheet, IEEE Int. AP-S Symp., Palo Alto CA, 1977.
  21. V. D. Agrawal and G. G. Wong, Helix Antenna for Multiple Access Array of TDRSS Spacecraft, TDRSS-77-331-107, TRW Defense and Space Systems Group, Redondo Beach CA, 1977, Report No..
  22. V. D. Agrawal, Grating Lobe Suppression in Phased Arrays by Subarray Rotation, Proc. IEEE, Vol. 66, pp. 347--349, 1978.
  23. V. D. Agrawal and T. C. Tong, Grating Lobe Suppression in Multiple Access Array of TDRSS Spacecraft, IEEE Int. AP-S Symp. Digest, pp. 178--181, Washington D.C., 1978.
  24. V. D. Agrawal, Selection of Element for a Scanned Array Antenna, Archiv fur Elektronik und Ubertragungstechnik (AEU), Vol. 32, pp. 493--495, 1978.
  25. V. D. Agrawal, When to Use Random Testing, IEEE Trans. Comput., Vol. C-27, pp. 1054--1055, 1978.
  26. V. D. Agrawal, Electrostatic Analog for Finding Nonintersecting Paths, IETE Student s Journal (India), Vol. 20, pp. 3--7, 1979.
  27. V. D. Agrawal and G. G. Wong, A High Performance Helical Element for Multiple Access Array on TDRSS Spacecraft, IEEE Int. AP-S Symp. Digest, pp. 481--484, Seattle Washington, 1979.
  28. V. D. Agrawal and W. A. Imbriale, Design of a Dichroic Cassegrain Subreflector, IEEE Trans. Ant. Prop., Vol. AP-27, pp. 466--473, 1979.
  29. V. D. Agrawal, Authors Reply to Comments on When to Use Random Testing, IEEE Trans. Comput., Vol. C-28, pp. 581, 1979.
  30. V. D. Agrawal, Comments on An Approach to Highly Integrated Computer Maintained Cellular Arrays, IEEE Trans. Comput., Vol. C-28, pp. 691--693, 1979.

    31. 1980-1989

  31. V. D. Agrawal and A. K. Bose and P. Kozak and H. N. Nham and E. Pacas-Skewes, A Mixed-Mode Simulator, Proc. 17th Des. Auto. Conf., pp. 618--625, Minneapolis Minnesota, June 23-25 1980.
  32. V. D. Agrawal, Information Theory in Digital Testing - A New Approach to Functional Test Pattern Generation, Proc. Int. Conf. Cir. Comput., pp. 928--931, Port Chester N.Y., October 1-3 1980.
  33. V. D. Agrawal, Random Test Generation - A Tutorial, Bell Syst. Conf. on Electronic Testing, pp. 9--11, Princeton N.J., October 14-16 1980.
  34. V. D. Agrawal and Y. T. Lo, Comments on Characterization of the Random Array Peak Sidelobes, IEEE Trans. Ant. Prop., Vol. AP-28, pp. 946--948, 1980.
  35. V. D. Agrawal and S. C. Seth and P. Agrawal, LSI Product Quality and Fault Coverage, Proc. 18th Des. Auto. Conf., pp. 196--203, Nashville TN, June 29-July 1 1981.
  36. V. D. Agrawal, An Information Theoretic Approach to Digital Testing, IEEE Trans. Comput., Vol. C-30, pp. 582--587, 1981.
  37. M. R. Mercer and V. D. Agrawal and C. M. Roman, An LSI Chip Designed for Testability, Bell System Conference on Electronic Testing, Princeton N.J., 1981.
  38. V. D. Agrawal, Sampling Techniques for Determining Fault Coverage in LSI Circuits, J. Digital Syst., Vol. V, pp. 189--202, Fall 1981.
  39. V. D. Agrawal, Emerging Roles of VLSI Testing, SEMICON Southwest, Dallas Texas, October 13-14 1981.
  40. M. R. Mercer and V. D. Agrawal and C. M. Roman, Test Generation for Highly Sequential Scan-testable Circuits through Logic Transformation, International Test Conference, Philadelphia PA, October 27-29 1981, (Digest of Papers pp. 561-565.) .
  41. S. C. Seth and V. D. Agrawal, Forecasting Reject Rate of Tested LSI Chips, IEEE Electron Device Letters, Vol. EDL-2, pp. 286--287, 1981.
  42. V. D. Agrawal and A. K. Bose and P. Kozak and H. N. Nham and E. Pacas-Skewes, Mixed-mode Simulation in the MOTIS System, J. Digital Syst., Vol. V, pp. 383--400, Winter 1981.
  43. V. D. Agrawal and S. C. Seth and P. Agrawal, Fault Coverage Requirements in Production Testing of LSI Circuits, IEEE J. Sol. St. Circ., Vol. SC-17, pp. 57--61, 1982.
  44. M. R. Mercer and V. D. Agrawal, Testability Strategies for Custom Polycell Designs, Computer Elements Workshop, New York N.Y., May 21-22 1982.
  45. V. D. Agrawal, Synchronous Path Analysis in MOS Circuit Simulator, Proc. 19th Des. Auto. Conf., pp. 629--635, Las Vegas Nevada, June 14-16 1982.
  46. S. C. Seth and V. D. Agrawal, Statistical Design Verification, 12th Int. Fault Tolerant Computing Symp., Santa Monica CA, June 22-24 1982, (Digest of Papers pp. 393-399.) .
  47. M. R. Mercer and V. D. Agrawal, Applications of Testability Measures in VLSI Design, Bell System Conference on Electronic Testing, pp. 52--58, Princeton N.J., October 5-7 1982.
  48. V. D. Agrawal and M. R. Mercer, Testability Measures - What Do They Tell Us?, Int. Test Conf., Philadelphia PA, November 16-18 1982, (Digest of Papers pp. 391-396.) .
  49. S. K. Jain and V. D. Agrawal, Statistical Fault Analysis - A Technique for Estimating Fault Coverage through Good Circuit Simulation, IEEE Design for Testability Workshop, Vail CO, April 12-14 1983.
  50. S. K. Jain and V. D. Agrawal, Test Generation for MOS Circuits using D -Algorithm, Proc. 20th Des. Auto. Conf., pp. 64--70, Miami Beach Florida, 1983.
  51. V. D. Agrawal and S. K. Jain and D. M. Singer, Design for Testability - Tutorial, Bell Syst. Conf. on Electronic Testing, Princeton N.J., 1983.
  52. S. C. Seth and V. D. Agrawal, Characterizing the LSI Yield Equation from Chip Test Data, Proc. Int. Conf. Circ. Comp., pp. 556--559, New York N.Y., Sept. 28-Oct. 1 1982, (Also IEEE Trans. CAD Vol. CAD-3 pp. 123-126 April 1984.) .
  53. M. R. Mercer and V. D. Agrawal, A Novel Clocking Technique for VLSI Circuit Testability, IEEE J. Sol. St. Circ., Vol. SC-19, pp. 207--212, 1984.
  54. S. K. Jain and M. Weisel and V. D. Agrawal, Scan Overhead Optimization in Standard Cell Design, IEEE Design for Testability Workshop, Vail CO, April 24-26 1984.
  55. V. D. Agrawal and S. K. Jain and D. M. Singer, Automation in Design for Testability, Custom Integrated Circuits Conf., pp. 159--163, Rochester N.Y., May 21-23 1984.
  56. S. M. Reddy and M. K. Reddy and V. D. Agrawal, Robust Tests for Stuck-open Faults in CMOS Combinational Logic Circuits, Proc. 14th Int. Fault Tolerant Comp. Symp., pp. 44--49, Kissimmee Florida, June 20-22 1984.
  57. S. K. Jain and V. D. Agrawal, STAFAN An Alternative to Fault Simulation, Proc. ACM IEEE 21st Des. Auto. Conf., pp. 18--23, Albuquerque N.M., June 25-27 1984.
  58. A. E. Dunlop and V. D. Agrawal and D. N. Deutsch and M. F. Jukl and P. Kozak and M. Wiesel, Chip Layout Optimization using Critical Path Weighting, Proc. ACM IEEE 21st Des. Auto. Conf., pp. 133--136, Albuquerque N.M., June 25-27 1984.
  59. S. M. Reddy and V. D. Agrawal and S. K. Jain, A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection, Proc. ACM IEEE 21st Des. Auto. Conf., pp. 504--509, Albuquerque N.M., June 25-27 1984.
  60. V. D. Agrawal and S. K. Jain and D. M. Singer, A CAD System for Design for Testability, VLSI Design, Vol. V, pp. 46--54, 1984.
  61. V. D. Agrawal, Will Testability Analysis Replace Fault Simulation, Panel Discussion Int. Test Conf., Philadelphia PA, 1984.
  62. V. D. Agrawal, Computer-Aids in VLSI Design, IEEE Int. Conf. on Computers Systems and Signal Processing, Bangalore India, December 10-12 1984.
  63. S. K. Jain and V. D. Agrawal, Statistical Fault Analysis, IEEE Design Test of Computers, Vol. 2, pp. 38--44, 1985.
  64. V. D. Agrawal and S. H. C. Poon, VLSI Design Process, ACM Computer Science Conference, pp. 74--78, New Orleans Louisiana, March 12-14 1985.
  65. S. C. Seth and V. D. Agrawal, Cutting Chip Testing Costs, IEEE Spectrum, Vol. 22, pp. 38--45, 1985.
  66. S. K. Jain and V. D. Agrawal, Modeling and Test Generation Algorithms for MOS Circuits, IEEE Trans. Comput., Vol. C-34, pp. 426--433, 1985.
  67. V. D. Agrawal and S. C. Seth and C. C. Chuang, Probabilistically Guided Test Generation, Int. Symp. on Circuits and Systems, pp. 687--690, Kyoto Japan, 1985.
  68. S. C. Seth and L. Pan and V. D. Agrawal, PREDICT - Probabilistic Estimation of Digital Circuit Testability, Fault Tolerant Computing Symposium, pp. 220--225, Ann Arbor Michigan, June 19-21 1985.
  69. P. Agrawal and V. D. Agrawal and N. N. Biswas, Multiple Output Minimization, Proc. of 22nd Design Automation Conference, pp. 674--680, Las Vegas Nevada, June 24-26 1985.
  70. S. K. Jain and V. D. Agrawal, Clarifying Statistical Fault Analysis - Authors Reply, IEEE Design Test, Vol. 2, pp. 7--8, 1985.
  71. V. D. Agrawal and S. C. Seth, Probabilistic Testability, Int. Conf. on Computer Design, pp. 562--565, Port Chester NY, 1985.
  72. V. D. Agrawal, Stafan Takes a Middle Course (Position Statement), International Test Conference, Philadelphia PA, 1985.
  73. S. C. Seth and V. D. Agrawal, A Review of Testing of VLSI Devices, IETE Tech. Review, Vol. 1, pp. 363--374, 1985.
  74. V. D. Agrawal, VLSI Testing, First International Workshop on VLSI Design, Madras India, December 18-26 1985.
  75. S. C. Seth and B. B. Bhattacharya and V. D. Agrawal, An Exact Analysis for Efficient Computation of Random-Pattern Testability in Combinational Circuits, Fault Tolerant Computing Symposium, pp. 318--323, Vienna Austria, July 1-3 1986.
  76. T. Lin and V. D. Agrawal, A Test Generator for Scan-Design VLSI Circuits, AT&T Conference on Electronic Testing, pp. 23.1--23.7, Jamesburg NJ, 1986.
  77. V. D. Agrawal and D. D. Johnson, Logic Modeling of PLA Faults, Int. Conf. on Computer Design, pp. 86--88, Port Chester NY, 1986.
  78. N. C. E. Srinivas and V. D. Agrawal, PROVE Prolog Based Verifier, Int. Conf. on Computer-Aided Design, pp. 306--309, Santa Clara CA, 1986.
  79. V. D. Agrawal and K. T. Cheng and D. D. Johnson and T. Lin, A Complete Solution to the Partial Scan Problem, Proc. Int. Test Conference, pp. 44--51, Washington D.C., 1987.
  80. V. D. Agrawal and K. T. Cheng, A Simulation-Based Directed Search Method for Test Generation, Proc. Int. Conf. on Computer Design (ICCD), pp. 48--51, Port Chester NY, 1987.
  81. V. D. Agrawal and K. T. Cheng and P. Agrawal, Use of a Concurrent Fault Simulator for Test Vector Generation, Proc. AT&T Conf. on Electronic Testing, pp. 23--28, Princeton NJ, 1987.
  82. N. C. E. Srinivas and V. D. Agrawal, Formal Verification of Digital Circuits using Hybrid Simulation, Circuits and Devices, Vol. 4, pp. 19--27, 1988.
  83. V. D. Agrawal and K. T. Cheng and D. D. Johnson and T. Lin, Designing Circuits with Partial Scan, IEEE Design Test of Computers, Vol. 5, pp. 8--15, 1988.
  84. V. D. Agrawal, Statistical Testing, Testing and Diagnosis of VLSI and ULSI, Ed. F. Lombardi and M. Sami, pp. 33--47, Kluwer Academic Publishers, Dordrecht The Netherlands, 1988.
  85. V. D. Agrawal and K. T. Cheng, Threshold-Value Simulation and Test Generation, Testing and Diagnosis of VLSI and ULSI, Ed. F. Lombardi and M. Sami, pp. 311--323, Kluwer Academic Publishers, Dordrecht The Netherlands, 1988.
  86. V. D. Agrawal and K. T. Cheng and P. Agrawal, CONTEST A Concurrent Test Generator for Sequential Circuits, Proc. Des. Auto. Conf., pp. 84--89, Anaheim CA, 1988.
  87. K. T. Cheng and V. D. Agrawal and E. S. Kuh, A Sequential Circuit Test Generator Using Threshold-Value Simulation, Digest of Papers Fault-Tolerant Computing Symposium (FTCS-18), pp. 24--29, Tokyo Japan, 1988.
  88. V. D. Agrawal and S. C. Seth, Test Generation for VLSI Chips, IEEE Computer Society Press, Los Alamitos CA, 1988.
  89. V. D. Agrawal and H. Farhat and S. C. Seth, Test Generation by Fault Sampling, Proc. Int. Conf. on Computer Design (ICCD-88), pp. 58--61, Rye Brook NY, 1988.
  90. V. D. Agrawal, Testability and Productivity - The Merging of the Two Goals, Proc. TECHCON 88 (An SRC Conference), pp. 137--140, Dallas TX, 1988.
  91. V. D. Agrawal and S. C. Seth, On a Relationship Between Fault Coverage and Circuit Testability, Proc. AT&T Conf. Electronic Testing, pp. 16.1--16.6, Princeton NJ, 1988.
  92. P. Agrawal and V. D. Agrawal and K. T. Cheng, Fault Simulation in MARS, Proc. AT&T Conf. Electronic Testing, pp. 40.1--40.9, Princeton NJ, 1988.
  93. S. T. Chakradhar and M. L. Bushnell and V. D. Agrawal, Automatic Test Generation Using Neural Networks, Proc. Int. Conf. on Computer-Aided Design (ICCAD-88), pp. 416--419, Santa Clara CA, 1988.
  94. S. C. Seth and V. D. Agrawal, On the Probability of Fault Occurrence, Defect and Fault Tolerance in VLSI Systems, Ed. I. Koren, pp. 47--52, Plenum Publishing Corp., 1989.
  95. V. D. Agrawal and S. M. Reddy, Fault Modeling and Test Generation, VLSI Handbook, Ed. J. DiGiacomo, pp. Chapter 8, McGraw-Hill, New York, 1989.
  96. V. D. Agrawal, Design Automation Expert Opinion, IEEE Spectrum, Vol. 26, pp. 36--37, 1989.
  97. V. D. Agrawal and K. T. Cheng and P. Agrawal, A Directed Search Method for Test Generation Using a Concurrent Simulator, IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 131--138, 1989.
  98. S. C. Seth and V. D. Agrawal and H. Farhat, A Theory of Testability with Application to Fault Coverage Analysis, Proc. European Test Conference, pp. 139--143, Paris France, 1989.
  99. S. C. Seth and V. D. Agrawal, A New Model for Computation of Probabilistic Testability in Combinational Circuits, INTEGRATION The VLSI Journal, Vol. 7, pp. 49--75, 1989.
  100. K. T. Cheng and V. D. Agrawal, Concurrent Test Generation and Design for Testability, Proc. Int. Symp. Circ. Syst. (ISCAS), pp. 1935--1938, Portland Oregon, 1989.
  101. K. T. Cheng and V. D. Agrawal, Unified Methods for VLSI Simulation and Test Generation, Kluwer Academic Publishers, Boston, 1989.
  102. K. T. Cheng and V. D. Agrawal, An Economical Scan Design for Sequential Logic Test Generation, Proc. 19th Fault-Tolerant Computing Symposium (FTCS-19), pp. 28--35, 1989.
  103. P. Agrawal and V. D. Agrawal and K. T. Cheng and R. Tutundjian, Fault Simulation in a Pipelined Multiprocessor System, Proc. Int. Test Conf, pp. 727--734, Washington DC, 1989.
  104. K. T. Cheng and V. D. Agrawal, State Assignment for Initializable Synthesis, Proc. Int. Conf. Computer-Aided Design (ICCAD-89), pp. 212--215, Santa Clara CA, 1989.
  105. K. T. Cheng and V. D. Agrawal, Design of Sequential Machines for Efficient Test Generation, Proc. Int. Conf. Computer-Aided Design (ICCAD-89), pp. 358--361, Santa Clara CA, 1989.

    106. 1990-1999

  106. V. D. Agrawal and K. T. Cheng, An Architecture for Synthesis of Testable Finite State Machines, Proc. First European Design Automation Conference, pp. 612--616, Glasgow UK, 1990.
  107. K. T. Cheng and V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Trans. Comput., Vol. 39, pp. 544--548, 1990.
  108. S. C. Seth and V. D. Agrawal and H. Farhat, A Statistical Theory of Digital Circuit Testability, IEEE Trans. Comput., Vol. 39, pp. 582--586, 1990.
  109. P. Agrawal and V. D. Agrawal, Can Logic Simulators Handle Bidirectionality and Charge Sharing?, Proc. Int. Symp. Circ. Syst. (ISCAS), pp. 411--414, New Orleans, 1990.
  110. K. T. Cheng and V. D. Agrawal, Synthesis of Testable Finite State Machines, Proc. Int. Symp. Circ. Syst. (ISCAS), pp. 3114--3117, New Orleans, 1990.
  111. S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell, Automatic Test Generation using Quadratic 0-1 Programming, Proc. 27th ACM IEEE Des. Autom. Conf., pp. 654--659, Orlando FL, 1990.
  112. V. D. Agrawal and K. T. Cheng, Test Function Specification in Synthesis, Proc. 27th ACM IEEE Des. Autom. Conf., pp. 235--240, Orlando FL, 1990.
  113. K. T. Cheng and V. D. Agrawal, An Entropy Measure for the Complexity of Multi-Output Boolean Functions, Proc. 27th ACM IEEE Des. Autom. Conf., pp. 302--305, Orlando FL, 1990.
  114. S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell, Polynomial Time Solvable Fault Detection Problems, Proc. 20th Fault-Tolerant Computing Symposium (FTCS-20), pp. 56--63, Newcastle-upon-Tyne UK, 1990.
  115. V. D. Agrawal and H. Kato, Fault Sampling Revisited, IEEE Design Test of Computers, Vol. 7, pp. 32--35, 1990.
  116. S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell, Toward Massively Parallel Automatic Test Generation, IEEE Trans. CAD, Vol. 9, pp. 981--994, 1990.
  117. D. V. Das and S. C. Seth and P. T. Wagner and J. C. Anderson and V. D. Agrawal, An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited, Proc. Int. Test Conf., pp. 712--720, 1990.
  118. S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell, Neural Net and Boolean Satisfiability Models of Logic Circuits, IEEE Design Test of Computers, Vol. 7, pp. 54--57, 1990.
  119. V. D. Agrawal and K. T. Cheng, Finite State Machine Synthesis with Embedded Test Function, Electronic Testing: Theory and Applications (JETTA), Vol. 1, 3, pp. 221--228, 1990.
  120. S. T. Chakradhar and V. D. Agrawal, Statistical Performance of a Parallel Processing System, Proc. ISMM Int. Conf. on Parallel and Distributed Computing and Systems, pp. 212--216, 1990.
  121. S. T. Chakradhar and V. D. Agrawal, Logic Simulation and Parallel Processing, Proc. Int. Conf. on CAD (ICCAD), pp. 496--499, 1990.
  122. S. T. Chakradhar and V. D. Agrawal, Performance Estimation in a Massively Parallel System, Proc. Supercomputing 90, pp. 306--313, 1990.
  123. K. T. Cheng and V. D. Agrawal and E. S. Kuh, A Simulation-Based Method for Generating Tests for Sequential Circuits, IEEE Trans. on Computers, Vol. 39, pp. 1456--1463, 1990.
  124. V. D. Agrawal and S. C. Seth and J. S. Deogun, Design for Testability and Test Generation with Two Clocks, Proc. 4th CSI IEEE International Symp. on VLSI Design, pp. 112--117, 1991.
  125. S. T. Chakradhar and V. D. Agrawal, A Novel VLSI Solution to a Difficult Graph Problem, Proc. 4th CSI IEEE International Symp. on VLSI Design, pp. 124--129, 1991.
  126. S. T. Chakradhar and V. D. Agrawal, Neural Models and Algorithms for Digital Testing, Kluwer Academic Publishers, Boston, 1991.
  127. K. T. Cheng and V. D. Agrawal, Methods for Synthesizing Testable Sequential Circuits, AT&T Technical Journal, Vol. 70, pp. 64--86, 1991.
  128. S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell, On Test Generation Using Neural Computers, Intl. J. Computer Aided VLSI Design, Vol. 3, pp. 241--257, 1991.
  129. K. T. Cheng and V. D. Agrawal, State Assignment for Testable Design, Int. J. Computer Aided VLSI Design, Vol. 3, pp. 291--307, 1991.
  130. S. Bhawmik and C. J. Lin and K. T. Cheng and V. D. Agrawal, PASCANT A Partial Scan and Test Generation System, Proc. Custom Integrated Circ. Conf., 1991.
  131. S. T. Chakradhar and V. D. Agrawal, A Transitive Closure Based Algorithm for Test Generation, Proc. 28th Design Automation Conf., 1991.
  132. P. C. Sardeshmukh and V. D. Agrawal, Filtering of SEM Voltage Contrast Images, 3rd European Conf. Electron and Optical Beam Testing, Como Italy, 1991.
  133. J. Villoldo and P. Agrawal and V. D. Agrawal, Stafan Algorithms for MOS Circuits, Proc. Intl. Conf. Computer Design, pp. 56--59, 1991.
  134. V. D. Agrawal, Design and Test --- The Two Sides of a Coin, Proc. Intl. Conf. Computer Design, pp. 12, 1991.
  135. D. V. Das and S. C. Seth and V. D. Agrawal, Estimating the Quality of Manufactured Digital Sequential Circuits, Proc. Intl. Test Conf., pp. 210--217, 1991.
  136. P. Agrawal and V. D. Agrawal and S. C. Seth, A New Method for Generating Tests for Delay Faults in Non-Scan Circuits, Proc. 5th Intl. Conf. VLSI Design, pp. 4--11, 1992.
  137. J. Jacob and V. D. Agrawal, Functional Test Generation for Sequential Circuits, Proc. 5th Intl. Conf. VLSI Design, pp. 17--24, 1992.
  138. V. D. Agrawal, Technology Forecast and Weather Prediction (Keynote Address), Proc. 2nd Great Lakes Symp. on VLSI, pp. 1--2, 1992.
  139. K. T. Cheng and V. D. Agrawal, Initializability Considerations in Sequential Machine Synthesis, IEEE Trans. Comput., Vol. 41, pp. 374--379, 1992.
  140. S. T. Chakradhar and M. A. Iyer and V. D. Agrawal, Energy Minimization Based Delay Testing, Proc. European Design Autom. Conf., pp. 280--284, 1992.
  141. S. T. Chakradhar and S. Kanjilal and V. D. Agrawal, A Synthesis for Testability Technique for PLA -Based Finite State Machines, Proc. European Design Autom. Conf., pp. 361--365, 1992.
  142. E. Ulrich and K. P. Lentz and J. Arabian and M. Gustin and V. D. Agrawal and P. L. Montessoro, The Comparative and Concurrent Simulation of Discrete-Event Experiments, Jour. Electronic Testing: Theory and Applic. (JETTA), Vol. 3, pp. 107--118, 1992.
  143. J. Jacob and V. D. Agrawal, Multiple Fault Detection in Two-Level Multi-Output Circuits, Jour. Electronic Testing: Theory and Applic. (JETTA), Vol. 3, pp. 171--173, 1992.
  144. T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell, Delay Fault Models and Test Generation for Random Logic Sequential Circuits, Proc. Design Autom. Conf., pp. 165--172, 1992.
  145. D. Bhattacharya and P. Agrawal and V. D. Agrawal, Delay Fault Test Generation for Scan hold Circuits using Boolean Expressions, Proc. Design Autom. Conf., pp. 159--164, 1992.
  146. S. T. Chakradhar and S. Kanjilal and V. D. Agrawal, Finite State Machine Synthesis with Fault Tolerant Test Function, Proc. Design Autom. Conf., pp. 562--567, 1992, (also it Jour. Electronic Testing: Theory and Applic. (JETTA) vol. 4 pp. 57-69 February 1993) .
  147. M. K. Srinivas and J. Jacob and V. D. Agrawal, Finite State Machine Testing Based on Growth and Disappearance Faults, Proc. 22nd Fault-Tolerant Comput. Symp., pp. 238--245, 1992.
  148. P. Agrawal and V. D. Agrawal and S. C. Seth, DynaTAPP: Dynamic Timing Analysis With Partial Path Activation in Sequential Circuits, Proc. EURO-DAC, pp. 138--141, 1992.
  149. V. D. Agrawal and S. T. Chakradhar, Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems, IEEE Trans. Parallel and Distr. Syst., Vol. 3, pp. 739--746, 1992.
  150. T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell, Path Delay Simulation Algorithms for Sequential Circuits, Proc. First Asian Test Symp., pp. 52--56, 1992.
  151. S. Bose and P. Agrawal and V. D. Agrawal, A Path Delay Fault Simulator for Sequential Circuits, Proc. 6th Intermational Conf. VLSI Design, pp. 269--274, 1993.
  152. P. Agrawal and V. D. Agrawal and S. C. Seth, Generating Tests for Delay Faults in Nonscan Circuits, IEEE Design Test of Computers, Vol. 10, pp. 20--28, 1993.
  153. V. D. Agrawal and C. R. Kime and K. K. Saluja, A Tutorial on Built-In Self-Test Part 1: Principles, IEEE Design Test of Computers, Vol. 10, pp. 73--82, 1993.
  154. K. L. Einspahr and S. C. Seth and V. D. Agrawal, Clock Partitioning for Testability, Proc. 3rd Great Lakes Symp. VLSI, pp. 42--46, 1993.
  155. S. Bose and P. Agrawal and V. D. Agrawal, Delay Fault Testability Evaluation through Timing Simulation, Proc. 3rd Great Lakes Symp. VLSI, pp. 18--21, 1993.
  156. V. D. Agrawal and T. J. Chakraborty, Partial Scan Testing with Single Clock Control, Proc. IEEE VLSI Test Symp., pp. 313--315, 1993.
  157. V. D. Agrawal and S. T. Chakradhar, Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits, Proc. European Test Conf., pp. 249--253, 1993.
  158. V. D. Agrawal, A Tale of Two Designs: the Cheapest and the most Economic (Keynote Talk), Second International Workshop on the Economics of Design Test and Manufacturing, 1993, (Also Proc. 12th AT&T Conference on Electronic Testing September 1993 pp. 241-244) .
  159. S. T. Chakradhar and V. D. Agrawal and S. G. Rothweiler, A Transitive Closure Algorithm for Test Generation, IEEE Trans. CAD, Vol. 12, pp. 1015--1028, 1993.
  160. V. D. Agrawal and C. R. Kime and K. K. Saluja, A Tutorial on Built-In Self-Test Part 2: Applications, IEEE Design Test of Computers, Vol. 10, pp. 69--77, 1993.
  161. P. Agrawal and V. D. Agrawal and J. Villoldo, Sequential Circuit Test Generation on a Distributed System, Proc. 29th Design Autom. Conf., pp. 107--111, 1993.
  162. T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell, Design for Testability for Path Delay Faults in Sequential Circuits, Proc. 29th Design Autom. Conf., pp. 453--457, 1993.
  163. P. Agrawal and V. D. Agrawal and J. Villoldo, Test Pattern Generation for Sequential Circuits on a Network of Workstations, Proc. 2nd International Symp. High Performance Distr. Comput., pp. 114--120, 1993.
  164. S. Bose and P. Agrawal and V. D. Agrawal, The Optimistic Update Theorem for Path Delay Testing of Sequential Circuits, Jour. Electronic Testing: Theory and Applic., Vol. 4, pp. 285--290, 1993.
  165. S. Kanjilal and S. T. Chakradhar and V. D. Agrawal, Test Function Embedding Algorithms with Application to Interconnected Finite State Machines, Proc. EURO-DAC, pp. 219--224, 1993.
  166. S. Bose and P. Agrawal and V. D. Agrawal, Logic Systems for Path Delay Test Generation, Proc. EURO-DAC, pp. 200--205, 1993.
  167. S. Bose and P. Agrawal and V. D. Agrawal, Generation of Compact Delay Tests by Multiple Path Activation, Proc. International Test Conf., pp. 714--723, 1993.
  168. S. Kanjilal and S. T. Chakradhar and V. D. Agrawal, A Synthesis Approach to Design for Testability, Proc. International Test Conf., pp. 754--763, 1993.
  169. P. R. Sureshkumar and J. Jacob and M. K. Srinivas and V. D. Agrawal, FASSAD Fault Simulation With Sensitivities and Depth-First Propagation, Proc. 2nd Asian Test Symp., pp. 66--71, 1993.
  170. S. Bose and P. Agrawal and V. D. Agrawal, Path Delay Fault Simulation of Sequential Circuits, IEEE Trans. VLSI Systems, Vol. 1, pp. 453--461, 1993.
  171. D.V. Das and S. C. Seth and V. D. Agrawal, Accurate Computation of Field Reject Ratio Based on Fault Latency, IEEE Trans. VLSI Systems, Vol. 1, pp. 537--545, 1993.
  172. S. Kanjilal and S. T. Chakradhar and V. D. Agrawal, A Test Function Architecture for Interconnected Finite State Machines, Proc. 7th International Conference VLSI Design, pp. 113--116, 1994.
  173. R.M. Chou and K.K. Saluja and V. D. Agrawal, Power Constraint Scheduling of Tests, Proc. 7th International Conference VLSI Design, pp. 271--274, 1994.
  174. P. R. Sureshkumar and J. Jacob and M. K. Srinivas and V. D. Agrawal, An Improved Deductive Fault Simulator, Proc. 7th International Conference VLSI Design, pp. 307--310, 1994.
  175. E. G. Ulrich and V. D. Agrawal and J. H. Arabian, Concurrent and Comparative Discrete Event Simulation, Kluwer Academic Publishers, Boston, 1994.
  176. S. T. Chakradhar and V. D. Agrawal and M. L. Bushnell, Energy Minimization and Design for Testability, Jour. Electronic Testing: Theory and Applic., Vol. 5, pp. 55--64, 1994.
  177. T. J. Chakraborty and V. D. Agrawal, Delay Independent Initialization of Sequential Circuits, Proc. 4th Great Lakes Symp. VLSI Design, pp. 228--230, 1994.
  178. K. Heragu and V. D. Agrawal and M. L. Bushnell, FACTS Fault Coverage Estimation by Test Vector Sampling, Proc. 12th IEEE VLSI Test Symp., pp. 266--271, 1994.
  179. K. Heragu and M. L. Bushnell and V. D. Agrawal, An Efficient Path Delay Fault Coverage Estimator, Proc. 31st Design Automation Conf., pp. 516--521, 1994.
  180. S. T. Chakradhar and A. Balakrishnan and V. D. Agrawal, An Exact Algorithm for Selecting Partial Scan Flip-Flops, Proc. 31st Design Automation Conf., pp. 81--86, 1994, (Also Jour. Electronic Testing: Theory and Applic. vol. 7 pp. 83-93 August-October 1995.) .
  181. V. D. Agrawal and C. J. Lin and P. Rutkowski and S. Wu and Y. Zorian, Built-In Self-Test for Digital ICs, AT&T Tech. Jour., Vol. 73, pp. 30--39, 1994.
  182. T. J. Chakraborty and V. D. Agrawal, Test Generation and Fault Simulation Algorithms for Sequential Circuits with Embedded RAMs, Proc. Third Asian Test Symp., pp. 2--7, 1994.
  183. P. Agrawal and V. D. Agrawal and M. L. Bushnell and J. Sienicki, Superlinear Speedup in Multiprocessing Environment, Proc. First International Workshop on Parallel Processing, pp. 261--265, 1994.
  184. J. Sienicki and M. L. Bushnell and P. Agrawal and V. D. Agrawal, An Asynchronous Algorithm for Sequential Circuit Test Generation on a Network of Workstations, Proc. 8th International Conf. VLSI Design, pp. 36--41, 1995.
  185. T. J. Chakraborty and V. D. Agrawal, Robust Testing for Stuck-at Faults, Proc. 8th International Conf. VLSI Design, pp. 42--46, 1995.
  186. M. K. Srinivas and J. Jacob and V. D. Agrawal, Functional Test Generation for Non-Scan Sequential Circuits, Proc. 8th International Conf. VLSI Design, pp. 47--52, 1995.
  187. A. K. Majhi and J. Jacob and L. M. Patnaik and V. D. Agrawal, An Efficient Automatic Test Generation System for Path Delay Faults in Combinational Circuits, Proc. 8th International Conf. VLSI Design, pp. 161--165, 1995.
  188. K. Heragu and V. D. Agrawal and M. L. Bushnell, Statistical Methods for Delay Fault Coverage Analysis, Proc. 8th International Conf. VLSI Design, pp. 166--170, 1995.
  189. D. Bhattacharya and P. Agrawal and V. D. Agrawal, Test Generation for Path Delay Faults using Binary Decision Diagrams, IEEE Trans. Computers, Vol. 44, pp. 434--447, 1995.
  190. S. T. Chakradhar and S.G. Rothweiler and V. D. Agrawal, Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives, Proc. 13th IEEE VLSI Test Symp., pp. 12--19, April-May 1995.
  191. T. J. Chakraborty and V. D. Agrawal, Simulation of At-Speed Tests for Stuck-at Faults, Proc. 13th IEEE VLSI Test Symp., pp. 216--220, April-May 1995.
  192. K. Heragu and V. D. Agrawal and M. L. Bushnell, Fault Coverage Estimation by Test Vector Sampling, IEEE Trans. CAD, Vol. 14, pp. 590--596, 1995, (Correction August 1995 p. 1037) .
  193. S. T. Chakradhar and M.A. Iyer and V. D. Agrawal, Energy Models for Delay Testing, IEEE Trans. CAD, Vol. 14, pp. 728--739, 1995.
  194. S. Kanjilal and S. T. Chakradhar and V. D. Agrawal, Test Function Embedding Algorithms with Application to Interconnected Finite State Machines, IEEE Trans. CAD, Vol. 14, pp. 1115--1127, 1995.
  195. V. D. Agrawal and S. T. Chakradhar, Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits, IEEE Trans. CAD, Vol. 14, pp. 1155--1160, 1995.
  196. J. Sienicki and M. L. Bushnell and P. Agrawal and V. D. Agrawal, An Adaptive Distributed Algorithm for Sequential Circuit Test Generation, Proc. EURO-DAC, pp. 236--241, 1995.
  197. S. Kanjilal and S. T. Chakradhar and V. D. Agrawal, A Partition and Resynthesis Approach to Testable Design of Large Circuits, IEEE Trans. CAD, Vol. 14, pp. 1268--1276, 1995.
  198. M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal, Classification and Test Generation for Path-Delay Faults using Single Stuck-Fault Tests, Proc. International Test Conf., pp. 139--148, 1995.
  199. V. D. Agrawal and T. J. Chakraborty, High-Performance Circuit Testing with Slow-Speed Testers, Proc. International Test Conf., pp. 302--310, 1995.
  200. M. K. Srinivas and V. D. Agrawal and M. L. Bushnell, Functional Test Generation for Path Delay Faults, Proc. Fourth Asian Test Symp., pp. 339--345, 1995.
  201. S. Bose and V. D. Agrawal, Sequential Logic Path Delay Test Generation by Symbolic Analysis, Proc. Fourth Asian Test Symp., pp. 353--359, 1995.
  202. V. D. Agrawal, Science Technology and the Indian Society A Keynote Talk, Proc. 9th International Conf. VLSI Design, pp. 6--8, 1996.
  203. T. J. Chakraborty and V. D. Agrawal, Design for High Speed Testability of Stuck-at Faults, Proc. 9th International Conf. VLSI Design, pp. 53--56, 1996.
  204. L. Pappu and M. L. Bushnell and V. D. Agrawal, Statistical Path-Delay Fault Coverage Estimation for Synchronous Sequential Circuits, Proc. 9th International Conf. VLSI Design, pp. 290--295, 1996.
  205. V. D. Agrawal and D. Lee, Characteristic Polynomial Method for Verification and Test of Combinational Circuits, Proc. 9th International Conf. VLSI Design, pp. 341--342, 1996.
  206. A. K. Majhi and J. Jacob and L. M. Patnaik and V. D. Agrawal, On Test Coverage of Path-Delay Faults, Proc. 9th International Conf. VLSI Design, pp. 418--421, 1996.
  207. K. Heragu and J. H. Patel and V. D. Agrawal, Improving Accuracy in Path-Delay Fault Coverage Estimation, Proc. 9th International Conf. VLSI Design, pp. 422--425, 1996.
  208. M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal, Parallel Pattern Concurrent Fault Simulation of Path-Delay Faults with Single-Input Change Tests, Proc. 9th International Conf. VLSI Design, pp. 426--431, 1996.
  209. K. L. Einspahr and S. C. Seth and V. D. Agrawal, Improving Circuit Testability by Clock Control, Proc. Sixth Great Lakes Symp. on VLSI, pp. 288--293, 1996.
  210. K. Heragu and J. H. Patel and V. D. Agrawal, Segment Delay Faults: A New Fault Model, Proc. 14th IEEE VLSI Test Symp., pp. 32--39, April-May 1996.
  211. M. K. Srinivas and J. Jacob and V. D. Agrawal, Functional Test Generation for Synchronous Sequential Circuits, IEEE Trans. on CAD, Vol. 15, pp. 831--843, 1996.
  212. V. D. Agrawal, Testing in a Mixed-Signal World, Proc. 9th Annual IEEE International ASIC Conf., pp. 241--244, 1996.
  213. M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal, An Exact Non-Enumerative Fault Simulator for Path-Delay Faults, Proc. International Test Conf., pp. 276--285, 1996.
  214. V. D. Agrawal and R.D. Blanton and M. Damiani, Synthesis of Self-Testing Finite State Machines from High-Level Specification, Proc. International Test Conf., pp. 757--766, 1996.
  215. K. Heragu and J. H. Patel and V. D. Agrawal, SIGMA A Simulator for Segment Delay Faults, Proc. IEEE ACM International Conf. on CAD, pp. 502--508, 1996.
  216. V. D. Agrawal and M. L. Bushnell and Q. Lin, Redundancy Identification using Transitive Closure, Proc. Fifth Asian Test Symp., pp. 4--9, 1996.
  217. M. K. Srinivas and M. L. Bushnell and V. D. Agrawal, Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation, Proc. 10th International Conf. on VLSI Design, pp. 88--94, 1997.
  218. V. D. Agrawal, Low-Power Design by Hazard Filtering, Proc. 10th International Conf. on VLSI Design, pp. 193--197, 1997.
  219. J. Jacob and P. S. Sivakumar and V. D. Agrawal, Adder and Comparator Synthesis with Exclusive- OR Transform of Inputs, Proc. 10th International Conf. on VLSI Design, pp. 514--515, 1997.
  220. S. T. Chakradhar and V. D. Agrawal, VLSI Design, Encyclopedia of Microcomputers, Ed. A. Kent and J. G. Williams, pp. 97--111, Marcel Dekker Inc., New York, 1997, (Volume 20) .
  221. R. M. Chou and K. K. Saluja and V. D. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Trans. VLSI Systems, Vol. 5, 2, pp. 175--185, 1997.
  222. K. Heragu and V. D. Agrawal and M. L. Bushnell and J. H. Patel, Improving a Nonenumerative Method to Estimate Path Delay Fault Coverage, IEEE Trans. CAD, Vol. 16, 7, pp. 759--762, 1997.
  223. M. A. Gharaybeh and M. L. Bushnell and V. D. Agrawal, Classification and Test Generation for Path-Delay Faults Using Single Stuck-at Fault Tests, J. Electronic Testing: Theory and Applications, Vol. 11, 1, pp. 55--67, 1997.
  224. T. J. Chakraborty and V. D. Agrawal and M. L. Bushnell, On Variable Clock Methods for Path Delay Testing of Sequential Circuits, IEEE Trans. CAD, Vol. 16, 11, pp. 1237--1249, 1997.
  225. S. T. Chakradhar and S. G. Rothweiler and V. D. Agrawal, Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives, IEEE Trans. CAD, Vol. 16, 11, pp. 1370--1377, 1997.
  226. S. Bose and V. D. Agrawal and T. G. Szymanski, Proc. International Test Conf., pp. 982-991, 1997.
  227. T. J. Chakraborty and V. D. Agrawal, Effective Path Selection for Delay Fault Testing of Sequential Circuits, Proc. International Test Conf., pp. 998--1003, 1997.
  228. K. Heragu and J. H. Patel and V. D. Agrawal, Fast Identification of Untestable Delay Faults Using Implications, Proc. International Conf. CAD, pp. 642--647, 1997.
  229. P. Chavda and J. Jacob and V. D. Agrawal, Optimizing Logic Using Boolean Transforms, Proc. 11th International Conf. VLSI Design, pp. 218--221, 1998.
  230. A. K. Majhi and V. D. Agrawal, Mixed-Signal Test, Proc. 11th International Conf. VLSI Design, pp. 285--288, 1998.
  231. A. K. Majhi and V. D. Agrawal, Tutorial: Delay Fault Models and Coverage, Proc. 11th International Conf. VLSI Design, pp. 364--369, 1998.
  232. S. Majumder and V. D. Agrawal and M. L. Bushnell, Path Delay Testing: Variable-Clock Versus Rated-Clock, Proc. 11th International Conf. VLSI Design, pp. 470--475, 1998.
  233. V. D. Agrawal and S. C. Seth, Mutually Disjoint Signals and Probability Calculation in Digital Circuits, Proc. 8th Great Lakes Symp. VLSI, pp. 307--312, 1998.
  234. M. A. Gharaybeh and M. L. Bushnell and V. D. Agrawal, The Path-Status Graph with Application to Delay Fault Simulation, IEEE Trans. CAD, Vol. 17, 4, pp. 324--332, 1998.
  235. V. D. Agrawal, Test Education for VLSI Systems Design Engineers, Proc. Computer Soc. Workshop on VLSI, pp. 62--64, 1998.
  236. S. Majumder and V. D. Agrawal and M. L. Bushnell, On Delay-Untestable Paths and Stuck-Fault Redundancy, Proc. 16th IEEE VLSI Test Symp., pp. 194--199, 1998.
  237. S. Bose and P. Agrawal and V. D. Agrawal, A Rated-Clock Test Method for Path Delay Faults, IEEE Trans. VLSI Systems, Vol. 6, 2, pp. 323--331, 1998.
  238. L. Pappu and M. L. Bushnell and V. D. Agrawal and S. Mandyam-Komar, Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits, J. Electronic Testing: Theory and Applications, Vol. 12, 3, pp. 239--254, 1998.
  239. V. D. Agrawal and D. Lee and H. Wo z niakowski, Numerical Computation of Characteristic Polynomials of Boolean Functions and its Applications, Numerical Algorithms, Vol. 17, pp. 261--278, 1998.
  240. S. Bose and P. Agrawal and V. D. Agrawal, Deriving Logic Systems for Path Delay Test Generation, IEEE Trans. Computers, Vol. 47, 8, pp. 829--846, 1998.
  241. M.A. Gharaybeh and M. L. Bushnell and V. D. Agrawal, A Parallel-Vector Concurrent-Fault Simulator and Generation of Single-Input-Change Tests for Path-Delay Faults, IEEE Trans. CAD, Vol. 17, 9, pp. 873--876, 1998.
  242. C. G. Parodi and V. D. Agrawal and M. L. Bushnell and S. Wu, A Non-Enumerative Path Delay Fault Simulator for Sequential Circuits, Proc. International Test Conf., pp. 934--943, 1998.
  243. M.A. Gharaybeh and V. D. Agrawal and M. L. Bushnell, False Path Removal Using Delay Fault Simulation, Proc. 7th IEEE Asian Test Symp., pp. 82--87, 1998.
  244. V. D. Agrawal, Design of Mixed-Signal Systems for Testability, Integration the VLSI J., Vol. 26, pp. 141--150, 1998.
  245. V. D. Agrawal and M. L. Bushnell and G. Parthasarathy and R. Ramadoss, Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method, Proc. 12th International Conf. VLSI Design, pp. 434--439, 1999.
  246. K. Heragu and J. H. Patel and V. D. Agrawal, A Test Generator for Segment Delay Faults, Proc. 12th International Conf. VLSI Design, pp. 484--491, 1999.
  247. S. Majumder and B. B. Bhattacharya and V. D. Agrawal and M. L. Bushnell, A Complete Characterization of Path Delay Faults through Stuck-at Faults, Proc. 12th International Conf. VLSI Design, pp. 492--497, 1999.
  248. Y. C. Kim and V. D. Agrawal and K. K. Saluja, A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability, Proc. 9th Great Lakes Symp. on VLSI, pp. 300--303, 1999.
  249. P. A. Thaker and V. D. Agrawal and M. E. Zaghloul, Validation Vector Grade ({VVG}): A New Coverage Metric for Validation and Test, Proc. 17th IEEE VLSI Test Symp., pp. 182--188, 1999.
  250. Q. Peng and V. D. Agrawal and J. Savir, On the Guaranteed Failing and Working Frequencies in Path Delay Fault Analysi, Proc. 16th IEEE Instrumentation and Measurement Technology Conf., pp. 1794--1799, 1999.