Patents
of Vishwani D. Agrawal
- U.S. Patent 4,493,077, awarded January 8, 1985
Scan Testable Integrated Circuit
(with M. R. Mercer)
- U.S. Patent 5,043,986, awarded August 27, 1991
Method and Integrated Circuit Adapted for Partial Scan Testability
(with K.-T. Cheng)
- U.S. Patent 5,228,040, awarded July 13, 1993
Testable Implementations of Finite State Machines and Methods for Producing Them
(with K.-T. Cheng)
- U.S. Patent 5,257,268, awarded October 26, 1993
Cost-function Directed Search Method for Generating Tests for Sequential Logic Circuits
(with P. Agrawal and K.-T. Cheng)
- U.S. Patent 5,365,528, awarded November 15, 1994
Method for Testing Delay Faults in Non-Scan Sequential Circuits
(with T. J. Chakraborty)
- U.S. Patent 5,377,201, awarded December 27, 1994
A Transitive Closure Based Process for Generating Test Vectors for VLSI Circuits
(with S. T. Chakradhar)
- U.S. Patent 5,461,573, awarded October 24, 1995
VLSI Circuits Designed for Testability and Methods for Producing Them
(with S. T. Chakradhar and S. Kanjilal)
- U.S. Patent 5,499,249, awarded March 12, 1996
Method and Apparatus for Test Generation and Fault Simulation for Sequential
Circuits with Embedded Random Access Memories (RAMs)
(with T. J. Chakraborty)
- U.S. Patent 5,590,135, awarded December 31, 1996
Testing a Sequential Circuit
(with M. Abramovici, K.-T. Cheng and K. B. Rajan)
- U.S. Patent 5,606,567, awarded February 25, 1997
Delay Testing of High-Performance Digital Components by a Slow-Speed Tester
(with T. J. Chakraborty)
- U.S. Patent 5,657,240, awarded August 12, 1997
Testing and Removal of Redundancies in VLSI Circuits with Non-Boolean Primitives
(with S. T. Chakradhar and S. G. Rothweiler)
- U.S. Patent 5,983,007, awarded November 9, 1999
Low Power Circuits Through Hazard Pulse Suppression
- U.S. Patent 6,131,181, awarded October 10, 2000
Method and System for Identifying Tested Path Delay Faults
(with M. L. Bushnell and M. A. Gharaybeh)
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