INDIAN INSTITUTE OF TECHNOLOGY - DELHI
FALL 2013 M.Tech. Course: Low Power Design
(CSV881, Special Module in Hardware Systems)
VI-LT2, Oct 21-31, 2013, 3:30-5:00PM, except Oct 26 (10:30AM-12:00PM)
Course Syllabus

Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE, Auburn University
Teaching Assistant: Sharat Chandra Varma, Bharti Bldg., Architecture Lab (505), anz088224@cse.iitd.ac.in

Grade sheet

EXAM: Take-home problems, assigned Nov 1, 2013, due Nov 6, 2013, by 5:00PM.
(to be emailed or submitted in hardcopy to Sharat at the location specified above.)

HOMEWORK: All submissions can be emailed or submitted in hardcopy to Sharat at the location specified above.
Homework 1, assigned Oct 22, due Oct 23.
Homework 2, assigned Oct 24, due Oct 25.
Homework 3, assigned Oct 26, due Oct 28.
Homework 4, assigned Oct 28, due Oct 30.
Homework 5, assigned Oct 28, due Oct 30.

LECTURES:
Lectures 1 and 2: Introduction, Oct 21, 2013
Lectures 3 and 4: Power Dissipation in CMOS Circuits, Oct 22, 2013
Lectures 5, 6, 7: Gate-Level Power Analysis, Oct 23-24, 2013
Lectures 8 and 9: Linear Programming - A Mathematical Optimization Technique, Oct 24-25, 2013
Lectures 10, 11, 12: Gate-Level Power Optimization, Oct 25-26, 2013
Lecture 13: Multicore Design for Low Power, Oct 28, 2013
Lectures 14, 15 and 16: Power-Constrained Testing, Oct 29, 2013

PREVIOUS OFFERINGS BY PROF. V. AGRAWAL:
Summer 2012 VLSI Testing, IIT Delhi, July 24 - Aug 3, 2012
Summer 2011 Low-Power Design of Digital VLSI Circuits, IIT Delhi, July 26 - Aug 6, 2011
Summer 2010 VLSI Testing, IIT Delhi, Aug 7-13, 2010
Summer 2009 VLSI Testing, IIT Delhi, July 30 - Aug 13, 2009