Additive Printed Electronics

Additive Printed Flexible Hybrid Electronics (FHE)
Area-Leader
Dr. Pradeep Lall (Research Leader)

Additively printed electronics are being increasingly explored in the realm of electronics manufacturing. Additive printed circuits have found their way into various aspects of manufacturing starting from achieving reliable traces to multi-layer circuits with micro-via, and now surface mount devices. Different technologies have their merits and demerits based on the conductive material properties, substrate, and the printer's capability to incorporate multiple materials simultaneously.  Printed electronics are rapidly increasing and competing with traditional ways of manufacturing electronics. Different aspects of the processes are already being taken over in order to avoid material wastage and reduce costs and and lead times. For example, printing technologies are very popular in depositing reliable and very fine conductive traces. Authors have developed process studies by using Aerosol Jet Printing technology in realizing multi-layer metallization with successive metal and dielectric layers and additively printing a donut micro-via. Additionally, the assembly of Surface Mount Devices (SMD) on flexible substrates also has recently been of interest to researchers.  In many formulations, additive print methods on low temperature substrates may not be compatible with traditional surface-mount processes. Newer low temperature interconnection methods and novel packaging architectures enabled through additive processes are being developed.  The conductive traces are printed for interconnection to devices producing lower inductance interconnects and the dielectric is printed using using selective print processes.

Packaging-Manufacturing Reliability and PHM

Packaging-Manufacturing Reliability and PHM
Area-Leader
Dr. Pradeep Lall (Research Leader)

Structural health monitoring techniques are usually used as non-destructive techniques for identifying the stability of electronic systems. The major techniques used for this include built-in self-test, which conducts tests on functionality, use of auxiliary devices, which provides warnings before before the critical component's failure, and the use of fuses and canaries. These systems have their advantages in identifying failure of components, but also have disadvantages in predicting or monitoring the condition of the system during operation. Common examples of structural health monitoring are carried out in infrastructural projects in which different sensors are used to monitor the condition by using statistical and machine learning methods.

Significant fields that also use condition and health monitoring techniques involve aerospace structural stability analysis, health monitoring of offshore drilling equipment, condition modeling of civil structures with varying load and time, and in disciplines such as biology, medicine, and psychology. The most useful techniques used for feature vector identification and structural health monitoring involve statistical analysis, particularly related to pattern recognition, and decision boundary detection algorithms, with machine learning techniques with neural networks, and artificial intelligence. Previous work in health monitoring from strain signals involves the use of frequency components of the signals combined with the use of statistical techniques to identify the different feature vectors in predicting failure. 

Prognostic Health Management for Electronics
Prognostics Health Management (PHM) is the interrogation of system state and the assessment of product survivability in deployed systems using non-destructive assessment of underlying damage. System health is generally assessed in the actual operating environment. The prior stress history to which the system may have been subjected may not be known in several cases. Prognostics Health Management is very different from reliability prediction, which often assumes pristine materials and uses models that require definitive specification of environmental loads.

Recently, PHM has emerged as a key enabling technology for providing an early warning of failure. Early warnings may be used to forecast planned maintenance and assess the potential for life extensions. PHM has been applied to machines, aircrafts, bridges, electronics, and bio-implantable systems. Avionic systems require ultra-high reliability operation with minimal downtime. Automotive safety features such as anti-lock braking, airbags, and collision avoidance systems depend on the electronics utilized for their performance and reliability. Implantable biological systems are often life sustaining in nature. Deployed electronic systems often may be subjected to multiple thermal environments. Thermal environments may change due to operational factors or changes in usage profiles. Decision support for re-deployment requires PHM-based methods for assessment of the operational readiness of electronic systems, which is based on accrued damage and residual life in the intended environment. PHM will enable self-cognizant systems capable of assessing their own real-time performance under actual usage conditions and adaptively trigger risk mitigation actions to virtually eliminate unplanned failures.

Shock and Vibration
Electronic equipment can be subjected to many different forms of vibration over a wide range of frequencies and acceleration levels. All electronic equipment will be subjected to some type of vibration during its lifetime. If the vibration is not due to an active association with a machine or a moving vehicle, then it may be due to transportation of equipment from a manufacturer to a customer. Vibration is usually considered to be an undesirable condition because it can produce many different types of failures in electronic equipment. Mechanical vibrations can have different sources. In vehicles such as automobiles, trucks, and trains, most of the vibration is due to the rough surfaces over which these vehicles travel. In airplanes, missiles, and rockets, the vibration is due to jet and rocket engines and aerodynamic buffeting. Portable electronic devices such as pagers, palm-top organizers, and compactly designed cell phones are also vulnerable to damage from mechanical shock and vibration. With an indadvertent drop from a desk or bump against a wall, components can collide and render the device inoperable. Over a period of time, the post-shock ringing vibration can fatigue boards and connectors, which creates hard to spot electrical problems. Therefore, the testing of the electronic assemblies should include shock and vibration analysis.

Portable products face the challenges of ever increasing functional density, shorter product cycles, and pressure to reduce costs. Increasing functional density has led to the explosive growth in chip scale package (CSP) usage. The expected life span for a portable product is short compared to many other product categories. However, portable products must survive multiple drops. The decreasing I/O pitch of CSPs, and the resulting smaller pads and solder joints, make the drop requirement more challenging. There are two approaches to improving drop reliability. The first approach involves altering the mechanical design of a product in order to minimize the shock and flexing of the printed circuit board that occurs when the product is dropped. The second approach involves utilizing underfills to mechanically reinforce the CSP solder joints. Consequently, the development of a robust mechanical design, capable of resisting multiple drops, is the preferred approach. Electronics inside of portable electronic products may be subjected from a few hundred Gs to thousands of Gs during an accidental drop from ear level (on average, approximately a 5 ft. drop height). The use of an experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin, is often not feasible because of product development cycle time and cost constraints. There is a fundamental need for understanding and predicting the electronic failure mechanics in shock and drop impact. Figure 1 shows the drop orientation of printed circuit board assembly in vertical and horizontal (JEDEC) orientations.

Transient dynamic deformation of the test boards is the wave propagation problem. The explicit finite element model of drop impact of the test board under zero-degree-JEDEC drop orientation is shown in Figure 2. The JEDEC specifications require that the PCB be mounted with packages facing downwards, and mounted on a rigid base with the help of four-corner standoffs. The peak acceleration for this test is 1500 Gs at 0.5 ms half-sine pulse. The transient drop event is modeled using the commercially available finite element code Abaqus ®.

Connector Reliability and Tin Whiskers

Connectors and System-Level Interconnects: Degradation and Wear Mechanisms

Connector and interconnect reliability is a critical factor in electronic and system level packaging. Harsh Environment applications present several challenges. Important areas for research include fretting degradation and tin whiskers.
Area-Leader
Dr. George T. Flowers (Research Leader)

Objectives

Investigate basic mechanisms of vibration-induced fretting corrosion

Investigate factors that influence tin whisker growth in lead free plating finishes for connector pins

Investigate failure mechanisms for pin connectors and high current/voltage connectors

Tin Whiskers

Mechanism of Tin Whisker Growth in Electronics

Tin whiskers are electrically conductive, single crystal eruptions that can grow from surfaces where tin is deposited on a substrate surface (Fig. 1). High aspect ratio Sn whiskers are typically 1-5 µm in diameter and between 1-500 µm in length. They present reliability problems for the electronics industry with ongoing reports of tin whisker induced failures, particularly in the satellite and defense sectors (Fig. 2). Further, the current worldwide initiative to reduce the use of lead (Pb) is driving the electronics industry to consider high tin alternatives to the widely used Sn-37Pb alloys used for plating and solder. Continuing reports of tin whisker induced failures coupled with the lack of an industry-accepted understanding of tin whisker growth and/or test methods to identify whisker-prone products has made blanket acceptance of pure tin plating a risky proposition for high reliability systems. Harsh environments may exacerbate the problem by causing thermal and/or mechanical stresses in tin coated surfaces, leading to the growth of tin whiskers and to tin whisker induced failures. A common failure mode for whisker-prone electronic systems is whisker bridging, which causes electrical shorts (Fig. 3-4).

In addition to applied studies of whisker mitigation work on field parts, AUERI is currently conducting experiments to elucidate the fundamental mechanisms of whisker growth. This work is needed to develop a detailed understanding of the physical mechanisms leading to initiation and growth of tin whiskers and to reduce whiskering in Pb-free electronic components. While tin whisker growth is believed to be largely mechanical, there is currently no general agreement on the mechanism governing the growth of tin whiskers.

Previous investigations on whiskering have been hampered by lack of a reproducible means of growing laboratory controlled Sn whiskers in a reasonable time frame. Whiskers often display a long (months and years) and unpredictable incubation period before significant growth occurs. A technological advance has been the ability to consistently grow whiskers in a reasonably short period of time by using sputtered thin films grown under a variety of controlled intrinsic film stress conditions. By using controlled amounts of background Ar gas during the sputtering process, we have been able to achieve films with varying degrees of compressive stress to aid in reproducible whisker production. In addition, sputtered films avoid the complications of electrodeposited films and, in addition, allow us to grow very thin films (~ 0.1 micrometer), which has enabled several key advances involving whisker growth.

Currently, we are investigating the role of calibrated, controlled humidity on whisker production and the role of electric fields in the whiskering process. Humidity is important due to the preponderance of studies which report enhanced whisker growth in the presence of oxygen. Further, in the cracked oxide theory of whisker growth, sufficient compressive stress is presumed to occur at positions of oxide weakness which are the locations of whisker emission. A unique viewpoint of the whisker surface oxide is afforded by in-situ, real-time scanning electron microscopy (SEM) observations of Sn whiskers during heating to temperatures greater than the melting point of Sn. As the Sn melts, the whiskers buckle, curl, and drain of liquid Sn, leaving behind a thin, solid, emptied tube of tin oxide with its higher melting point. With further electron-beam heating, the tin oxide tube frequently forms a coagulated spherical ball of material which is the final resting place of the dead whisker skeleton.

Flip Chip and Underfills

Flip Chip and Underfills
Area-Leader
Dr. Jeffrey Suhling (Research Leader)

While Flip Chip Ball Grid Array (FCBGA) has been used in consumer products, its use in automotive underhoods with unusually high temperatures and extensive thermal excursions is new. The degradation of material properties and their influence on the reliability of semiconductor packaging architectures is not well understood. Owing to the variations in the thermal expansion coefficient between the organic substrate and the die in thermal cycling, bumps can be subjected to shear strains. The underfill encapsulation between the substrate and die is used to provide greater mechanical support to the solder bumps and reduce plastic work during thermal excursions. FCBGAs are high I/O packages in which the robustness of the underfill is required over the operational life to prevent premature failure of the flip-chip solder interconnects.

Underfills are thermoset mechanical supportive materials used in the overall enhancement of Flip Chip (FC) and Chip-Scale Packages (CSP), which include applications in high end workstations, high performance CPUs, mobile phones (with 5G), AI technologies, SiP packages, microwave technological applications, and many other end user appliances. In addition to linking the chip to the substrate, underfill materials also provide mechanical protection to the solder bumps and a considerable improvement in solder fatigue resistance. During temperature instability, underfill provides uniformly spread and shortened solder ball strains life of a factor near or more than 10. Underfill material also serves as a barrier to the chip from outside influences such as moisture, radiation, shock, and vibration.

Objectives

Develop a Fundamental Understanding of the Influence of Package Design, Manufacturing, and Materials on the Reliability of Flip Chip Packaging in Harsh Environments

• Flip Chip on Laminate
• Flip Chip BGA packaging
• CSP (e.g., Redistributed Die, UltraCSP, etc.)

Measure and Predict the Reliability of Flip Chip Packaging

• Flip Chip on Laminate in Thermal Cycling and High Humidity Environments
• High End Microprocessor Packaging

Study Next Generation Materials

• Nano-Structured Underfills
• High reliability substrates (e.g., STABLCOR)
• Thermal Interface Materials
• Chip-Level Interconnects

Develop a Detailed Understanding of Underfill Behavior and Properties

• Material Behavior (Stress-Strain and Creep)
• Interfacial Adhesion and Failure Criteria
• Effects of Aging and Moisture Exposure

Harsh Electronics Systems and Manufacturing

Harsh Environment Electronic Systems
Area-Leader
Dr. S'ad Hamasha (Research Leader), Dr. Jeffrey C. Suhling (Research Leader)

In this research area, electronics technologies for base-plate operating temperatures over the range -40° to 165° C are being developed. The primary goals are to first understand high temperature related failure mechanisms and to then formulate approaches to extend high temperature service life. Substrate reliability and attachment materials are being studied for both metal-backed laminate and metal-backed ceramic substrate technologies. Potential commercial applications include mechatronic electronic modules that are embedded within the automotive engine block or transmission. Deliverables include design guidelines for material selection, processing recommendations, and reliability data.

Objectives

• To Study the Reliability of Lead-Free Solder Mixes with Different Doped Solder Pastes in Thermal Cycling Considering the Effect of:
  • PCB Surface Finish
  • Solder Sphere Alloy
  • Bi/non-Bi Solder Pastes
  • Isothermal Elevated Temperature Aging
• Components including:
  • Ball Grid Array (BGA)
  • Quad Flat No-Lead (QFN)
  • Surface Mount Resistor (SMR)
• Develop a Finite Model for the SBGA 304 Component Subjected to Thermal Cycling
• Characterize Mechanical and Thermal Properties of Different Layers/Parts of the Package
• Use the Measured Properties to Predict Reliability (Thermal Fatigue Life) of the SBGA Component
• Investigate the Effects of PCB Laminate (Megtron 6 and FR4) on the Reliability of the SBGA
• Correlate the Predicted Life with the Measured Experimental and Failure Analysis Results
• Study the Effect of Surface Finish on Various Doped Solder Joints' Reliability Based on Shear and Fatigue Testing
• Study and Compare the Cyclic Stress-Strain Behavior (Loop Area, Plastic Strain Range, and Peak Stress) of SAC305 (Sn-3.0Ag-0.5Cu) and SAC_Q (Sn-3.41Ag-0.52Cu-3.3Bi) Lead Free Solders
• Study the Degradation of the Stress-Strain Behavior (Elastic Modulus, Yield Stress, and Ultimate Strength) Occurring in Lead Free Solders Due to Mechanical Cycling
• Study the Degradation of the Creep Behavior Occurring in Lead Free Solders Due to Mechanical Cycling
• Visualize the Microstructural Evolution Occurring in a Fixed Region within a Lead Free Solder Specimen Subjected to Mechanical Cycling (Fatigue Testing)
• Understand the Fatigue Failure Mechanisms in SAC305 and SAC_Q (Bi-doped) Lead Free Solder Samples
• Investigate the Aging Effects on the Fatigue Failure of these Solder Alloys by Microstructure Based Approach

Lead Free Soldering

Lead Free Solders
Area-Leaders
Dr. Jeffrey Suhling (Research Leader)
Dr. Sa'd Hamasha (Research Leader)
Dr. Michael Bozack (Research Leader)

Lead free solder materials are widely used as interconnects in electronic assemblies. They are often subjected to different thermal exposures such as isothermal aging and/or thermal cycling during their service life in various applications such a well drilling, automotive power electronics, aerospace engines, and geothermal energy. Therefore, the evolutions of mechanical properties of lead-free solder joint materials subjected to different thermal exposure profiles are of great importance and need to be investigated.

Electronic packaging industries are focusing on the relability challenge in the automobile sector and smaller solder joints at other electronic devices. Efficient characteristics like light weight, high speed, and miniaturization are necessary for devices such as laptops, cell phones, digital cameras, automobiles, and others. For the sake of increased demand, smart device manufacturers are focusing on designing these devices to have an array of solder interconnects with reductions in pitch and height.

The reliability of electronic packages largely depends on the surrounding application and specific application of the devices. It can be compromised by early failure, which can be caused by thermal cycling, mechanical loading, and coefficient of thermal expansion mismatch, among others. Reliable solder joints under various thermal exposure profiles are a key enabler to achieving robust packages and high performance.

Objectives

• Investigate the Mechanical Behavior (Stress-Strain) Evolution of SAC+Bi Solder Material under Different Thermal Cycling Profiles
• Investigate the Uniaxial Tensile Properties of SAC305 at Very High Temperatures (up to 200 °C) and Different Strain Rates
• Compare the Mechanical Properties of SAC305 at Various Operating Temperatures and Aging Conditions to Examine Effect of and Storage to Very High Temperature
• Determine Anand Model Parameters Using Experimental Results Experimental Results
• Investigate the Correlation of Anand Viscoelastic Model and Experimental Results
• Study the Effects of High Temperature Aging on the Mechanical Behavior of Lead Free Solders
• Explore Microstructural Evolution of IMC Particles Due to High Temperature Aging
• Study the drop shock relationship of matched lead-free solder joints compared to SnPb
• Provide the Basic Constitutive Laws and Mechanical Properties of Different Lead Free Solder Materials for Use in Finite Element Reliability Simulations