INDIAN INSTITUTE OF TECHNOLOGY - DELHI
SUMMER 2011 M.Tech. Course: Low-Power Design of Digital VLSI Circuits
July 26 - August 6, 2011
Course Syllabus

Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE, Auburn University

Grade Sheet

EXAM (take home), assigned 2/8/11, due in class on 5/8/11.

HOMEWORKS (5):
Homework 1, assigned 27/7/11, due 29/7/11.
Homework 2, assigned 28/7/11, due 30/7/11.
Homework 3, assigned 30/7/11, due 2/8/11, website for possible download of an LP solver.
Homework 4, assigned 1/8/11, due 3/8/11.
Homework 5, assigned 3/8/11, due 4/8/11.

LECTURES (17):
Lecture 1: Introduction to Low Power, July 26, 2011
Lectures 2, 3, 4: Power Dissipation of CMOS Circuits, July 27-28, 2011
Lectures 5, 6, 7, 8: Gate Level Power Analysis, July 28-29, 2011
Lectures 9, 10: Linear Programming - A Mathematical Optimization Technique, July 30, 2011
Lectures 11, 12, 13, 14: Gate-Level Power Optimization, Aug 1-2, 2011
Lecture 15: Multicore Design for Low Power, Aug 3, 2011
. . . See a recent New York Times story.
. . . Reading assignment: H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam and F. Burger, "Dark Silicon and the End of Multicore Scaling," Proc. 38th Int. Symp. on Comp. Arch., June 2011.
Lectures 16, 17: Digital Testing and Power, Aug 4-5, 2011

PREVIOUS COURSE OFFERINGS AT IITD BY PROF. V. AGRAWAL:
Summer 2010 VLSI Testing, IIT Delhi, Aug 7-13, 2010
Summer 2009 VLSI Testing, IIT Delhi, July 30 - Aug 13, 2009