The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Spring 2008 schedule:

When: Wednesdays from 4-5:30PM (* indicates schedule changes)

Where: Broun Hall room 235 (** indicates location change)

Coordinator: Vishwani Agrawal

Invitation: If you are interested in presenting a seminar during Spring 2007, please contact the coordinator.

Notes: The following is a tentative schedule for Spring 2008. The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF file of the presentation slides.

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Jan. 16	No Seminar	Due to ECE Department Meeting
Jan. 23	Chuck Stroud	Built-In Self-Test of DSPs in Virtex-4 & Virtex-5 FPGAs
Feb. 1	Yiorgos Makris*, Yale University	A Non-Linear Neural Classifier and its Applications in Testing Analog/RF Circuits
Feb. 6	Vic Nelson	Computer-Aided Design: From Concept to Silicon
Feb. 13	Foster Dai	RFIC Design for Wireless, Radar and Space Applications
Feb. 20	Bogdan M. 'Dan' Wilamowski	Methods of Computational Intelligence
Feb. 27	Richard Jaeger**	Introduction to Software Defined Radio
Mar. 5	Jie Qin	Analog Functional Self-Test in Mixed-Signal Systems (PhD General Oral Exam)
Mar. 12	Fan Wang	Soft Error Rate Determination for Nanometer CMOS VLSI Circuits (Master's Thesis Defense)
Mar. 26	Sadasiva M. Rao	Advanced Electromagnetic Solvers for Interconnect and Package Modeling
Apr. 2	Xuefeng Yu	RFIC Design for Direct Digital Frequency Synthesis (PhD General Oral Exam)
Apr. 9	Jins Alexander	Dynamic Power Estimation with Process Variation Modeled as Min-Max Delay
Apr. 16	NATW08 Authors	Papers to be presented at 17th IEEE North Atlantic Test Workshop, May 14-15, 2008: Built-In Self-Test of Global Routing Resources . . . Yao, Built-In Test and Calibration . . . Jiang, Sequential Circuit BIST . . . Yogi, Built-In Self-Test of Programmable I/O Cells . . . Dutton
Apr. 23	Hillary Grimes	Reconvergent Fanout Analysis of Bounded Gate Delay Faults (Master's Thesis Defense)

Links to previous semesters of the VLSI Design & Test Seminar Series:

Spring 2008: Coordinator Vishwani Agrawal

Fall 2007: Coordinator Adit Singh

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud