The VLSI Design & Test Seminar Series
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950-001 (which may be repeated for up to 3 credits).

This seminar series sponsored by:

the Testing Group at Auburn:

Vishwani Agrawal - Design for Testability (DFT) and low-power design

Foster Dai - mixed-signal and analog design and testing

Vic Nelson - ASIC/FPGA testing and fault tolerance

Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)

Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2011 schedule:

When: Wednesdays from 4-5:30PM (* indicates schedule changes)

Where: Broun Hall room 235 (** indicates location change)

Coordinator: Vishwani Agrawal

Invitation: If you are interested in presenting a seminar during Fall 2011, please contact the coordinator.

Notes: The following is a tentative schedule for Fall 2011. The link under Speaker is to an abstract of the presentation and the link under Topic is to a pdf or ppt file of the presentation slides.

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Aug. 17	Hao Yu	Research on Advanced Learning Algorithms of Neural Networks (PhD Defense)
Aug. 24	Charles Stroud	Built-In Self-Test for Spartan-6 FieldProgrammable Gate Arrays (Logic & RAMs), Part I
Aug. 31	Alex Lusco	Evaluating the Digital Fault Coverage for a Mixed-Signal Built-In Self-Test (MS Defense)
Sep. 7	Charles Stroud	Built-In Self-Test for Spartan-6 FieldProgrammable Gate Arrays (Logic & RAMs), Part II
Sep. 14	Praveen Venkataramani	Test Power Reduction in Leading Edge IP Using Cadence Encounter Test ATPG (Summer Internship Experience at Texas Intruments)
Sep. 21	No Seminar	International Test Conference, Anaheim, CA, Sep. 18-23, 2011
Sep. 28	Vijay B. Sheshadri	Evaluating Impact of Soft Errors in an Embedded System (Summer Internship Experience at Texas Intruments)
Oct. 5	Victor Nelson	Computer-Aided ASIC Design: Concept to Silicon
Oct. 12	Alvin J. Joseph, IBM	Silicon Technology Solutions for Mobile Applications
Oct. 19	Mridula Allani	Polynomial-Time Algorithms for Designing Dual-Voltage Energy Efficient Circuits (MS Defense)
Oct. 26	Lixing Zhao	On Diagnosing Multiple Net-Faults in a Combinational Circuit (MS Defense)
Nov. 2	Neil Da Cunha Ahmed Faraz	Da Cunha: A Unified Program for Modifying Built-In Self-Test Architectures for Xilinx Field Programmable Gate Arrays (MEE Defense) Faraz: Evaluation of a Circuit Path Delay Tuning Technique for Nanometer CMOS (MEE Defense)
Nov. 9	Abhijit Chatterjee, Georgia Tech	Process and Environment-Adaptive "Self-Aware" Rf/Mixed-Signal Circuits and Systems
Nov. 16	Xi Qian	Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations
Nov. 23	No Seminar	Thanksgiving break
Thu. Dec. 1*, 4PM, Broun 113**	Bruce Kim, U. of Alabama	RADPro: Automatic Test Program Generation Tool for Mixed-Signal and RF IC Load Board

Links to previous semesters of the VLSI Design & Test Seminar Series:

Spring 2011: Coordinator Adit Singh

Fall 2010: Coordinator Adit Singh

Spring 2010: Coordinator Chuck Stroud

Fall 2009: Coordinator Vishwani Agrawal

Spring 2009: Coordinator Adit Singh

Fall 2008: Coordinator Chuck Stroud

Spring 2008: Coordinator Vishwani Agrawal

Fall 2007: Coordinator Adit Singh

Spring 2007: Coordinator Chuck Stroud

Fall 2006: Coordinator Adit Singh

Spring 2006: Coordinator Vishwani Agrawal

Fall 2005: Coordinator Chuck Stroud

Spring 2005: Coordinator Adit Singh

Fall 2004: Coordinator Chuck Stroud