ELEC 7770-001 Advanced VLSI Design
Spring 2010, MWF 3PM, Broun 102
Course Syllabus (Not updated for this offering) Grades

Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE

Course Website: www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Grade Sheet

FINAL EXAM:
Take-Home Exam, assigned May 4, 2010, due May 7, 2010, can be emailed until midnight

LECTURES:
Lecture 1: Introduction, 1/11/10
Lecture 2: VLSI Yield and Moore's Law, 1/13/10
. . . Gordon Moore's articles, 1965, 1975, 1995
Lecture 3: Verification, 1/15/10 . . .
. . . Choice of Tests for Verification and Equivalence Checking . . .
. . . Characteristic Polynomial Method for Verification . . .
. . . Boolean Satisfiability . . .
Lecture 4: Timing analysis and STA, 1/25/08 . . .
Lecture 5: Timing Verification and Optimization, 2/1/10
Lecture 6: Retiming, 2/5/10 . . .
Lecture 7: Constraint Graph and Retiming Solution, 2/10/10 . . .
Lecture 8: Clock Skew Problem, 2/19/10 . . .
Lecture 9: Linear Programming - A Mathematical Optimization Technique, 2/22/10 . . .
Lecture 10: A Linear Programming Solution to Clock Constraint Problem, 3/1/10
Lecture 11: Zero-Skew Clock Routing, 3/5/10
Lecture 12: Gate Sizing, 3/10/10
Lecture 13: RF Testing, 3/11/10 . . .
Lecture 14: Logic Synthesis, 4/9/10 . . .
Lecture 15: Soft Errors and Fault-Tolerant Design, 4/14/10 . . .
. . . Robust System Design with Built-In Soft-Error Resilience . . ., Computer, vol. 38, no. 2, pp. 43-52, February 2005
. . . The Byzantine Generals, by D. Dolev, L. Lamport, M. Pease and R. Shostak, Chapter 12, B. K. Bhargava (Ed.), Concurrency Control and Reliability in Distributed Systems, pp. 348-369 (Van Nostrand, 1987)
Lecture 16: Power and Ground, 4/26/10 . . .
Lecture 17: Interconnects and Crosstalk, 5/4/10

HOMEWORKS:
Homework 1, assigned 2/3/10, due 2/17/10
Homework 2, assigned 3/1/10, due 3/15/10
Homework 3, assigned 3/22/10, due 4/5/10
Homework 4: Reading assignment for the week, March 29 - April 2, 2010; one-page report due 4/5/10.
Please read the paper assigned to you and write an exactly one-page report on (a) the most important point the authors make, (b) the impact on the future, and (c) main roadblocks in widespread use. Search the literature and your page must contain at least one additional reference. (Click on student's name for report.)
Allani: R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu and M. Pedram,
Architectures for Silicon Nanoelectronics and Beyond, Computer, vol. 40, no. 1, pp. 25-33, January 2007.
Kona: T. Munakata, Beyond Silicon: New Computing Paradigms, Comm. ACM, vol. 50, no. 9, pp. 30-34, Sept. 2007.
Mangilipally: W. Robinett, G. S. Snider, P. J. Kuekes and S. Williams, Computing with a Trillion Crummy Components, Comm. ACM, vol. 50, no. 9, pp. 35-39, Sept. 2007.
Qian: J. Kong, Computation with Carbon Nanotube Devices, Comm. ACM, vol. 50, no. 9, pp. 40-42, Sept. 2007.
Rashid: R. Stadler, Molecular, Chemical and Organic Computing, Comm. ACM, vol. 50, no. 9, pp. 43-45, Sept. 2007.
Shanmugasundaram: M. T. Bohr, R. S. Chau, T. Ghani and K. Mistry, "The High-k Solution," IEEE Spectrum, vol. 44, no. 10, pp. 29-35, October 2007
Surgnier: J. H. Reif and T. H. Labean, Autonomous Programmable Biomolecular Devices using Self-Assembled DNA Nanostructures, Comm. ACM, vol. 50, no. 9, pp. 46-53, Sept. 2007.
Venkataramani: D. Bacon and D. Leung, Toward a World with Quantum Computers, Comm. ACM, vol. 50, no. 9, pp. 55-59, Sept. 2007.
Venkatasubramanian: H. Abdeldayem and D. A. Frazier, Optical Computing: Need and Challenge, Comm. ACM, vol. 50, no. 9, pp. 60-62, Sept. 2007.
Zhao: D. W. M. Marr and T. Munakata, Micro/Nanofluidic Computing, Comm. ACM, vol. 50, no. 9, pp. 64-68, Sept. 2007.

PROJECT: Assignment, final report due 4/30/10
Study of Process Variability on Performance and Power
Retiming to Convert Single Cycle to Pipelined Datapath
Verification of Elmore Delay Formula
Verilog HDL Based Simulation of Process Variance Among Integrated Circuits
Equivalent Faults in Synthesis and Testing
Synchronization in Asynchronously Communicating Digital Systems
Timing Simulation of 45nm Technology and Analysis of Gate Tunneling Currents in 90, 65, 45 and 32nm Technologies
Design of Clock Distribution Networks - Case Study
Study of Operation of Flip Flop in Subthreshold Region in 90nm Technology

PREVIOUS OFFERING BY PROF. V. AGRAWAL:
Spring 2008
Spring 2007