ELEC 5200-001/6200-001 Computer Architecture and Design
Spring 2007, MWF 11AM, Broun 306
Course Syllabus Final Grades Statistics
Instructor: Vishwani D. Agrawal, James J. Danaher Professor of ECE
Teaching Assistant: Khushboo Sheth, Broun 359, 844-1865, Consultation: MWF 12:00-1:00, TuTh 12:30-1:30
During the final week of classes, please send email to set up meeting.
January 8 and 10, 2007: Guest Lectures on VHDL by Professor Charles E. Stroud

EXAMS:
Test 1, 03/05/07, 11:00-11:50AM, Broun 306, books, notes and laptop are permitted Statistics
Test 2, 04/09/07, 11:00-11:50AM, Broun 306, books, notes and laptop are permitted Statistics
Final Exam, 05/02/07, 11:00AM-1:30PM, Broun 306, books, notes and laptop are permitted Statistics
Note: While the student is responsible for the entire syllabus, the final exam will be on three topics, namely, performance, pipelining, and cache memory, that were not included in previous tests.

HOMEWORKS:
Homework 1, problem, assigned 1/8/07, due 1/17/07.
Homework 2, problems, assigned 1/22/07, due 1/29/07.
Homework 3, problems, assigned 2/5/07, due 2/12/07.
Homework 4, problems, assigned 2/19/07, due 2/26/07.
Homework 5, problems, assigned 3/5/07, due 3/12/07.
Homework 6, problems, assigned 3/23/07, due 4/4/07.
Homework 7, problems, assigned 4/2/07, due 4/11/07.
Homework 8, problems, assigned 4/16/07, due 4/20/07.
Homework 9, problems, assigned 4/23/07, due 4/27/07.
Homework 10, problems, assigned 4/25/07, due 4/30/07.

PROJECT:
Part 1 - ISA, assigned 2/2/07, due 2/16/07
Part 2 - Datapath, assigned 2/2/07, due 3/21/07
Part 3 - Datapath Verification, assigned 3/16/07, due 4/6/07
Part 4 - Control Unit, assigned 3/16/07, due 4/13/07
Part 5 - Hardware Implementation, assigned 3/16/07, due 4/20/07
All demos have been completed as on 4/30/07
A Final Report (no longer than one page) due 5/1/07 by email. Include:
(a) What you learned from the project.
(b) What would you do differently next time.
(c) Your advice to others doing such a project.
Final Reports: 1 2 3 4 5 6 7 8
Useful files:
LeonardoSpectrum for Altera HDL Synthesis Manual
qsim_logic.vhd. Compile and add "qsim_logic.vhd" to your current working directory. This will enable the 'to_interger' and 'to_stdlogicvector' functions used in the other files.
regfile.vhd is the code for a register file.
trans.vhd contains the code for a transceiver (bus interface).
Files for Part 4:
test.c is a test program in C.
Files for Part 5:
Altera MegaWizard Plug-In Manager Manual.
Altera Quartus II and DE2 Manual.
Altera DE2 Pin Assignments.
RAM_init.mif, Memory initialization file.

LECTURES: See webpages of most recent years.

PREVIOUS OFFERINGS BY PROF. AGRAWAL:
Fall 2006 Fall 2005 Fall 2004