ELEC 5200-002/6200-002 Computer Architecture and Design
Fall 2006, MWF 11AM, Broun 306
Course Syllabus, Grading Sheet (Final), Grading Bar Chart

Test 1, 9/11/06, Broun 306, 11:00-11:50AM; test will be administered by Ms. Khushboo Sheth (office: B359, shethkh@auburn.edu)
Coverage: Chapters 1 and 2. Use of book, class notes, lecture slides, calculator, computer permitted. There will be no lecture on 9/8/06; please use the class time for preparation, Statistics.

Test 2, 10/25/06, Broun 306, 11:00-11:50AM; test will be administered by Ms. Khushboo Sheth (office: B359, shethkh@auburn.edu)
Coverage: Chapters 3 and 5. Use of book, class notes, lecture slides, calculator, computer permitted, Statistics.

Final Exam, 12/9/06, Broun 306, 11:00AM-1:30PM.
Coverage: All chapters of book covered in class and homeworks. Use of book, class notes, lecture slides, calculator, computer permitted.

HOMEWORKS:
Homework 1, assigned 8/21/06, due 8/28/06, Problems.
Homework 2, assigned 8/28/06, due 9/6/06, Problems.
Homework 3, assigned 9/18/06, due 9/25/06, Problems.
Homework 4, assigned 9/25/06, due 10/2/06, Problems.
Homework 5, assigned 10/9/06, due 10/16/06, Problems.
Homework 6, assigned 10/16/06, due 10/23/06, Problems.
Homework 7, assigned 10/23/06, due 10/30/06, Problems.
Homework 8, assigned 11/6/06, due 11/13/06, Problems.
Homework 9, assigned 12/1/06, due 12/6/06, Problems.

LECTURES: See webpages of most recent years.

PROJECT:
Part 1, assigned 9/13/06, due 10/4/06
Part 2, assigned 10/6/06, due 10/18/06
Part 3, assigned 10/30/06, due 11/8/06
Part 4, assigned 11/8/06, due 11/27/06
Part 5, assigned 11/20/06, due 12/4/06, demo 12/5/06 3:00PM
Note: At the end of Part 5 report, include a caefully thought-out conclusion page with a few lines on each (total no more than half a page), (1) what you learnt in this project and (2) what would you do differently if you were to do it again (your advice to future students).
Useful files:
LeonardoSpectrum for Altera HDL Synthesis Manual
qsim_logic.vhd. Compile and add "qsim_logic.vhd" to your current working directory. This will enable the 'to_interger' and 'to_stdlogicvector' functions used in the other files.
regfile.vhd is the code for a register file.
trans.vhd contains the code for a transceiver (bus interface).
Files for Part 4:
memory16.vhd is VHDL description of memory.
test.c is a test program in C.
Files for Part 5:
Altera MegaWizard Plug-In Manager Manual.
Altera Quartus II and DE2 Manual.
Altera DE2 Pin Assignments.
RAM_init.mif, Memory initialization file.

CLASS PRESENTATIONS:
Instructions: 20 minutes, 15 slides max, be simple, include main idea, definitions, history, examples, references.
Chen, Y-C, 10/27/06, Multiprocessors
Dantu, SSK, 10/27/06, Virtual Machines
Erikson, CG, 11/3/06, Redundant Arrays of Inexpensive Disks
Kim, K, 11/3/06, Pentium 4 and IA-32 ISA
Kongara, H, 11/10/06, PowerPC
Moon, DY, 11/15/06, Virtual Memory
Ramadoss, L, 11/17/06, Superscalars
Soundararajan, S, 11/17/06, IBM360 and Tomasulo's Algorithm

PREVIOUS OFFERINGS BY PROF. AGRAWAL:
Fall 2005 Fall 2004