The VLSI Design & Test Seminar Series, Spring 2006
seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.
The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series is sponsored by:
the Testing Group at Auburn:
Vishwani Agrawal - Design for Testability (DFT) and low-power design
Foster Dai - mixed-signal and analog design and testing
Vic Nelson - ASIC/FPGA testing and fault tolerance
Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)
Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Spring 2006 schedule:
When: Wednesdays from 4-5:30pm
Where: Broun Hall room 235
Coordinator: Dr. Vishwani Agrawal
Invitation: If you are interested in presenting a seminar during Spring 2006, please contact the coordinator.
Notes: The link under Speaker is to an abstract of the presentation and the link under Topic is to a PDF or powerpoint file of the presentation slides.

Date	Speaker (w/ link to abstract)	Topic (w/ link to presentation slides after seminar date)
Jan. 18	Sachin Dhingra and Sudheer Vemula	Current Research in BIST for FPGA Logic and I/O Buffers
Jan. 25	Alok S. Doshi (MS Thesis Defense)	Independence Fault Collapsing and Concurrent Test Generation
Feb. 1	Adit D. Singh	Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing
Feb. 8	Vishwani D. Agrawal	Multi-Core Parallelism for Low Power Design
Feb. 15	Victor P. Nelson	Automating the Concept-to-ASIC Design Process
Feb. 22	Charles E. Stroud	BISTory of FPGAs
Mar. 1	Bruce C. Kim, Univ. of Alabama	Built-In Self-Test for Radio Frequency System-On-Chip
Mar. 8	Nitin Yogi	High-Level Spectral ATPG for Gate-Level Circuits
Mar. 15	Soo-Young Lee	PYRAMID: A Hierarchical Approach to E-beam Proximity Effect Correction
Mar. 22	Sudheer Vemula	Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs
Apr. 5	Krishna Kavi, Univ. of North Texas, Denton, TX (CSEE Seminar), Broun 238	Billion Transistor Chips: How to Garner the Silicon Real-Estate for Improved Performance?
Apr. 12	Gefu Xu	Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
Apr. 19	Foster Dai	RFIC Design for Wireless Communications
Apr. 26	Daniel Milton and Jie Qin	1. BIST of Logic and Memory Resources in Virtex-4 FPGAs (DM) 2. Phase Delay in MAC-based Analog Functional Testing in Mixed-Signal Systems (JQ)

Spring 2006 Attendance Statistics
Links to previous semester's seminars:
Fall 2005: Coordinator Dr. Chuck Stroud
Spring 2005: Coordinator Dr. Adit Singh
Fall 2004: Coordinator Dr. Chuck Stroud