VLSI Design & Test Seminar Series

The VLSI Design & Test Seminar Series seeks to provide an open forum for various faculty, graduate and undergraduate students with research and development efforts in the area of design and test of VLSI systems, including application specific and programmable circuits in digital, analog, and mixed-signal microsystems. The goal is to promote further learning, discussion, and teamwork along with the conception and development of exciting new ideas.

The seminar series counts as a 1-credit course ELEC7950 (which may be repeated for up to 3 credits).

This seminar series sponsored by the Testing Group at Auburn:

  • Vishwani Agrawal - Design for Testability (DFT) and low-power design
  • Foster Dai - mixed-signal and analog design and testing
  • Vic Nelson - ASIC/FPGA testing and fault tolerance
  • Adit Singh - digital and mixed-signal VLSI design and Design for Testability (DFT)
  • Chuck Stroud - digital and mixed-signal Built-In Self-Test (BIST)

Fall 2008 schedule:

When:  Wednesdays from 4-5:30pm
Where:  Broun Hall room 235
Coordinator:  Chuck Stroud

Date

Speaker

Topic

Aug. 27

AUBIST Lab

Production System-Level Use of Built-In Self-Test of Virtex-4 & Virtex-5 FPGAs

Sept. 3

Jins Alexander

Simulation Based Power Estimation for Digital CMOS Technologies (MS Defense)

Sept. 10

Testing Faculty

Everything You Ever Wanted to Know About Graduate School But Were Afraid to Ask

Sept. 17

TBD

 

Sept. 24

Khushboo Sheth

A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management (MS Defense)

Oct. 1

TBD

 

Oct. 8

TBD

 

Oct. 15

Robert Chua

NVIDIA Mixed-Signal Testing and Production Test at NVIDIA

Oct. 22

Wei Jiang

Built-in Self-Calibration of On-chip DAC and ADC (ITC paper)

Oct. 29

No Seminar

International Test Conference Week

Nov. 5

Nitin Yogi

Sequential Circuit BIST Synthesis using Spectrum and Noise from ATPG (ATS presentation)

Nov. 12

Bradley Dutton

SEU Detection and Correction in FPGA Configuration Memories

Nov. 19

Chuck Stroud

Fail-Safe Design Assurance in FPGAs

Nov. 26

No Seminar

Thanksgiving Break

Dec. 3

Khushboo Sheth

A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management (MS Defense) plus Seminar Evaluation Forms

For more information please visit: http://www.eng.auburn.edu/~strouce/D&TSeminarF08.html